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📁 使用ModelSim对Altera设计进行功能仿真对于没有使用到Altera的MegaWizard或LPM的设计而言
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# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_ram_clear
# Refreshing C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_ram_register
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_ram_register
# Refreshing C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_ram_internal
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_ram_internal
# ** Warning: (vsim-3015) D:/prj_D/modelsim_demo/timing_sim/pll_ram_tb.v(92): [PCDPC] - Port size (1 or 1) does not match connection size (8) for port 'wr_en'.
#         Region: /pll_ram_tb/pll_ram_u1
# ** Warning: (vsim-3015) D:/prj_D/modelsim_demo/timing_sim/pll_ram_tb.v(92): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'data_in'.
#         Region: /pll_ram_tb/pll_ram_u1
# Refreshing C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix.PRIM_DFFE
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix.PRIM_DFFE
# Loading D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(41): Failed to find INSTANCE '/pll_ram_tb/rst~I/inst1'.
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(50): Failed to find INSTANCE '/pll_ram_tb/clk_in~I/inst1'.
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(59): Failed to find INSTANCE '/pll_ram_tb/pllx2_u1|altpll_component|pll'.
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(69): Failed to find INSTANCE '/pll_ram_tb/wr_en~I/inst1'.
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(78): Failed to find INSTANCE '/pll_ram_tb/wr_addr_rtl_0|wysi_counter|counter_cell[0]/lecomb'.
# ** Warning: (vsim-SDF-3432) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo: This file is probably applied to the wrong instance.
# Ignoring subsequent missing instances from this file.
# ** Warning: (vsim-SDF-3440) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo: Failed to find any of the 48 instances from this file.
# ** Warning: (vsim-SDF-3442) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo: Try instance '/pll_ram_tb/pll_ram_u1'. It contains all instance paths from this file.
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo".
#    Time: 0 ps  Iteration: 0  Region: /pll_ram_tb  File: D:/prj_D/modelsim_demo/timing_sim/pll_ram_tb.v
# Error loading design
vsim -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/220model -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/alt_vtl -sdftyp /=D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo work.pll_ram_tb
# vsim -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/220model -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/alt_vtl -sdftyp /=D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo work.pll_ram_tb 
# Loading work.pll_ram_tb
# Loading work.pll_ram
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_io
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_io_register
# Refreshing C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.and1
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.and1
# Refreshing C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.mux21
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.mux21
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_asynch_io
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_pll
# Refreshing C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.m_cntr
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.m_cntr
# Refreshing C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.n_cntr
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.n_cntr
# Refreshing C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.scale_cntr
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.scale_cntr
# Refreshing C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.pll_reg
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.pll_reg
# Refreshing C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.dffe
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.dffe
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_lcell
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_asynch_lcell
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_lcell_register
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_ram_block
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_ram_clear
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_ram_register
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_ram_internal
# ** Warning: (vsim-3015) D:/prj_D/modelsim_demo/timing_sim/pll_ram_tb.v(92): [PCDPC] - Port size (1 or 1) does not match connection size (8) for port 'wr_en'.
#         Region: /pll_ram_tb/pll_ram_u1
# ** Warning: (vsim-3015) D:/prj_D/modelsim_demo/timing_sim/pll_ram_tb.v(92): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'data_in'.
#         Region: /pll_ram_tb/pll_ram_u1
# Refreshing C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.PRIM_DFFE
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.PRIM_DFFE
# Loading D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(41): Failed to find INSTANCE '/pll_ram_tb/rst~I/inst1'.
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(50): Failed to find INSTANCE '/pll_ram_tb/clk_in~I/inst1'.
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(59): Failed to find INSTANCE '/pll_ram_tb/pllx2_u1|altpll_component|pll'.
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(69): Failed to find INSTANCE '/pll_ram_tb/wr_en~I/inst1'.
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(78): Failed to find INSTANCE '/pll_ram_tb/wr_addr_rtl_0|wysi_counter|counter_cell[0]/lecomb'.
# ** Warning: (vsim-SDF-3432) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo: This file is probably applied to the wrong instance.
# Ignoring subsequent missing instances from this file.
# ** Warning: (vsim-SDF-3440) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo: Failed to find any of the 48 instances from this file.
# ** Warning: (vsim-SDF-3442) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo: Try instance '/pll_ram_tb/pll_ram_u1'. It contains all instance paths from this file.
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo".
#    Time: 0 ps  Iteration: 0  Region: /pll_ram_tb  File: D:/prj_D/modelsim_demo/timing_sim/pll_ram_tb.v
# Error loading design
vsim -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/220model -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/alt_vtl -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratixgx_gxb -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/sgate -sdftyp /=D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo work.pll_ram_tb
# vsim -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/220model -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/alt_vtl -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratixgx_gxb -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/sgate -sdftyp /=D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo work.pll_ram_tb 
# Loading work.pll_ram_tb
# Loading work.pll_ram
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_io
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_io_register
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.and1
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.mux21
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_asynch_io
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_pll
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.m_cntr
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.n_cntr
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.scale_cntr
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.pll_reg
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.dffe
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_lcell
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_asynch_lcell
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_lcell_register
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_ram_block
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_ram_clear
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_ram_register
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.stratix_ram_internal
# ** Warning: (vsim-3015) D:/prj_D/modelsim_demo/timing_sim/pll_ram_tb.v(92): [PCDPC] - Port size (1 or 1) does not match connection size (8) for port 'wr_en'.
#         Region: /pll_ram_tb/pll_ram_u1
# ** Warning: (vsim-3015) D:/prj_D/modelsim_demo/timing_sim/pll_ram_tb.v(92): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'data_in'.
#         Region: /pll_ram_tb/pll_ram_u1
# Loading C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/stratix.PRIM_DFFE
# Loading D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(41): Failed to find INSTANCE '/pll_ram_tb/rst~I/inst1'.
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(50): Failed to find INSTANCE '/pll_ram_tb/clk_in~I/inst1'.
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(59): Failed to find INSTANCE '/pll_ram_tb/pllx2_u1|altpll_component|pll'.
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(69): Failed to find INSTANCE '/pll_ram_tb/wr_en~I/inst1'.
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(78): Failed to find INSTANCE '/pll_ram_tb/wr_addr_rtl_0|wysi_counter|counter_cell[0]/lecomb'.
# ** Warning: (vsim-SDF-3432) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo: This file is probably applied to the wrong instance.
# Ignoring subsequent missing instances from this file.
# ** Warning: (vsim-SDF-3440) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo: Failed to find any of the 48 instances from this file.
# ** Warning: (vsim-SDF-3442) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo: Try instance '/pll_ram_tb/pll_ram_u1'. It contains all instance paths from this file.
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo".
#    Time: 0 ps  Iteration: 0  Region: /pll_ram_tb  File: D:/prj_D/modelsim_demo/timing_sim/pll_ram_tb.v
# Error loading design
# Compile of stratix_atoms.v was successful.
# Compile of altera_mf.v was successful.
# Compile of 220model.v was successful.
# 3 compiles, 0 failed with no errors. 
vsim -sdftyp /=D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo work.pll_ram_tb
# vsim -sdftyp /=D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo work.pll_ram_tb 
# Loading work.pll_ram_tb
# Loading work.pll_ram
# Loading work.stratix_io
# Loading work.stratix_io_register
# Loading work.and1
# Loading work.mux21
# Loading work.stratix_asynch_io
# Loading work.stratix_pll
# Loading work.m_cntr
# Loading work.n_cntr
# Loading work.scale_cntr
# Loading work.pll_reg
# Loading work.dffe
# Loading work.stratix_lcell
# Loading work.stratix_asynch_lcell
# Loading work.stratix_lcell_register
# Loading work.stratix_ram_block
# Loading work.stratix_ram_clear
# Loading work.stratix_ram_register
# Loading work.stratix_ram_internal
# ** Warning: (vsim-3015) D:/prj_D/modelsim_demo/timing_sim/pll_ram_tb.v(92): [PCDPC] - Port size (1 or 1) does not match connection size (8) for port 'wr_en'.
#         Region: /pll_ram_tb/pll_ram_u1
# ** Warning: (vsim-3015) D:/prj_D/modelsim_demo/timing_sim/pll_ram_tb.v(92): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port 'data_in'.
#         Region: /pll_ram_tb/pll_ram_u1
# Loading work.PRIM_DFFE
# Loading D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(41): Failed to find INSTANCE '/pll_ram_tb/rst~I/inst1'.
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(50): Failed to find INSTANCE '/pll_ram_tb/clk_in~I/inst1'.
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(59): Failed to find INSTANCE '/pll_ram_tb/pllx2_u1|altpll_component|pll'.
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(69): Failed to find INSTANCE '/pll_ram_tb/wr_en~I/inst1'.
# ** Error: (vsim-SDF-3250) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo(78): Failed to find INSTANCE '/pll_ram_tb/wr_addr_rtl_0|wysi_counter|counter_cell[0]/lecomb'.
# ** Warning: (vsim-SDF-3432) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo: This file is probably applied to the wrong instance.
# Ignoring subsequent missing instances from this file.
# ** Warning: (vsim-SDF-3440) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo: Failed to find any of the 48 instances from this file.
# ** Warning: (vsim-SDF-3442) D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo: Try instance '/pll_ram_tb/pll_ram_u1'. It contains all instance paths from this file.
# ** Error: (vsim-SDF-3445) Failed to parse SDF file "D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo".
#    Time: 0 ps  Iteration: 0  Region: /pll_ram_tb  File: D:/prj_D/modelsim_demo/timing_sim/pll_ram_tb.v
# Error loading design
# Compile of sgate.v was successful.
# Compile of nopli.v was successful.
# Compile of hcstratix_atoms.v was successful.
# 3 compiles, 0 failed with no errors. 
vsim -sdftyp /=D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.
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