pll_ram.tan.rpt

使用ModelSim对Altera设计进行功能仿真 对于没有使用到Altera的MegaWizard或LPM的设计而言

; 8.675 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[3]                                                  ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_address_reg3 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.702 ns                  ; 1.027 ns                ;
; 8.690 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[4]                                                  ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_address_reg4 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.702 ns                  ; 1.012 ns                ;
; 8.782 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[3]                                                  ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[3]                                                  ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.814 ns                  ; 1.032 ns                ;
; 8.790 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[2]                                                  ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[2]                                                  ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.814 ns                  ; 1.024 ns                ;
; 8.903 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]                                                  ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]                                                  ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.814 ns                  ; 0.911 ns                ;
; 9.149 ns ; Restricted to 450.05 MHz ( period = 2.22 ns ) ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[4]                                                  ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[4]                                                  ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.814 ns                  ; 0.665 ns                ;
+----------+-----------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tsu                                                                                                                                                                               ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack ; Required tsu ; Actual tsu ; From       ; To                                                                                                                    ; To Clock ;
+-------+--------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------+----------+
; N/A   ; None         ; 6.369 ns   ; wr_en      ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]                                                  ; clk_in   ;
; N/A   ; None         ; 6.281 ns   ; wr_en      ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1]                                                  ; clk_in   ;
; N/A   ; None         ; 6.280 ns   ; wr_en      ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[2]                                                  ; clk_in   ;
; N/A   ; None         ; 6.280 ns   ; wr_en      ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[3]                                                  ; clk_in   ;
; N/A   ; None         ; 6.279 ns   ; wr_en      ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[4]                                                  ; clk_in   ;
; N/A   ; None         ; 6.276 ns   ; wr_en      ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_we_reg       ; clk_in   ;
; N/A   ; None         ; 6.237 ns   ; rd_addr[4] ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg4 ; clk_in   ;
; N/A   ; None         ; 6.220 ns   ; rd_addr[0] ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg0 ; clk_in   ;
; N/A   ; None         ; 6.218 ns   ; rd_addr[2] ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg2 ; clk_in   ;
; N/A   ; None         ; 6.215 ns   ; data_in[2] ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg2  ; clk_in   ;
; N/A   ; None         ; 6.209 ns   ; rd_en      ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_re_reg       ; clk_in   ;
; N/A   ; None         ; 6.176 ns   ; data_in[5] ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg5  ; clk_in   ;
; N/A   ; None         ; 6.084 ns   ; data_in[6] ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg6  ; clk_in   ;
; N/A   ; None         ; 6.057 ns   ; rd_addr[3] ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg3 ; clk_in   ;
; N/A   ; None         ; 6.026 ns   ; rd_addr[1] ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg1 ; clk_in   ;
; N/A   ; None         ; 5.861 ns   ; data_in[1] ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg1  ; clk_in   ;
; N/A   ; None         ; 5.859 ns   ; data_in[3] ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg3  ; clk_in   ;
; N/A   ; None         ; 5.857 ns   ; data_in[4] ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg4  ; clk_in   ;
; N/A   ; None         ; 5.851 ns   ; data_in[0] ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0  ; clk_in   ;
; N/A   ; None         ; 5.845 ns   ; data_in[7] ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg7  ; clk_in   ;
; N/A   ; None         ; 3.441 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_address_reg0 ; clk_in   ;
; N/A   ; None         ; 3.441 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_address_reg1 ; clk_in   ;
; N/A   ; None         ; 3.441 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_address_reg2 ; clk_in   ;
; N/A   ; None         ; 3.441 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_address_reg3 ; clk_in   ;
; N/A   ; None         ; 3.441 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_address_reg4 ; clk_in   ;
; N/A   ; None         ; 3.425 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0  ; clk_in   ;
; N/A   ; None         ; 3.425 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg1  ; clk_in   ;
; N/A   ; None         ; 3.425 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg2  ; clk_in   ;
; N/A   ; None         ; 3.425 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg3  ; clk_in   ;
; N/A   ; None         ; 3.425 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg4  ; clk_in   ;
; N/A   ; None         ; 3.425 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg5  ; clk_in   ;
; N/A   ; None         ; 3.425 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg6  ; clk_in   ;
; N/A   ; None         ; 3.425 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg7  ; clk_in   ;
; N/A   ; None         ; 3.417 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg0 ; clk_in   ;
; N/A   ; None         ; 3.417 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg1 ; clk_in   ;
; N/A   ; None         ; 3.417 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg2 ; clk_in   ;
; N/A   ; None         ; 3.417 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg3 ; clk_in   ;
; N/A   ; None         ; 3.417 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg4 ; clk_in   ;
; N/A   ; None         ; 3.387 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_re_reg       ; clk_in   ;
; N/A   ; None         ; 3.335 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_we_reg       ; clk_in   ;
; N/A   ; None         ; 3.320 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[0]                          ; clk_in   ;