dianzhen.tan.qmsg

基于FPGA的8*8点阵控制

{ "Info" "ITDB_TSU_RESULT" "dianzhen_out:inst2\|a\[0\] boma_4 clk 3.317 ns register " "Info: tsu for register \"dianzhen_out:inst2\|a\[0\]\" (data pin = \"boma_4\", clock pin = \"clk\") is 3.317 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.156 ns + Longest pin register " "Info: + Longest pin to register delay is 15.156 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns boma_4 1 PIN PIN_121 17 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_121; Fanout = 17; PIN Node = 'boma_4'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { boma_4 } "NODE_NAME" } } { "dianzhen.bdf" "" { Schematic "D:/altera/72/quartus/projects/dianzhen/dianzhen.bdf" { { 184 -16 152 200 "boma_4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.495 ns) + CELL(0.590 ns) 7.560 ns dianzhen_out:inst2\|a~8680 2 COMB LC_X20_Y8_N8 10 " "Info: 2: + IC(5.495 ns) + CELL(0.590 ns) = 7.560 ns; Loc. = LC_X20_Y8_N8; Fanout = 10; COMB Node = 'dianzhen_out:inst2\|a~8680'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.085 ns" { boma_4 dianzhen_out:inst2|a~8680 } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.090 ns) + CELL(0.442 ns) 10.092 ns dianzhen_out:inst2\|a\[7\]~8727 3 COMB LC_X18_Y6_N7 1 " "Info: 3: + IC(2.090 ns) + CELL(0.442 ns) = 10.092 ns; Loc. = LC_X18_Y6_N7; Fanout = 1; COMB Node = 'dianzhen_out:inst2\|a\[7\]~8727'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.532 ns" { dianzhen_out:inst2|a~8680 dianzhen_out:inst2|a[7]~8727 } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.452 ns) + CELL(0.292 ns) 10.836 ns dianzhen_out:inst2\|a\[7\]~8729 4 COMB LC_X18_Y6_N0 1 " "Info: 4: + IC(0.452 ns) + CELL(0.292 ns) = 10.836 ns; Loc. = LC_X18_Y6_N0; Fanout = 1; COMB Node = 'dianzhen_out:inst2\|a\[7\]~8729'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.744 ns" { dianzhen_out:inst2|a[7]~8727 dianzhen_out:inst2|a[7]~8729 } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.216 ns) + CELL(0.590 ns) 12.642 ns dianzhen_out:inst2\|a\[7\]~8737 5 COMB LC_X18_Y7_N2 8 " "Info: 5: + IC(1.216 ns) + CELL(0.590 ns) = 12.642 ns; Loc. = LC_X18_Y7_N2; Fanout = 8; COMB Node = 'dianzhen_out:inst2\|a\[7\]~8737'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.806 ns" { dianzhen_out:inst2|a[7]~8729 dianzhen_out:inst2|a[7]~8737 } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.647 ns) + CELL(0.867 ns) 15.156 ns dianzhen_out:inst2\|a\[0\] 6 REG LC_X21_Y5_N2 1 " "Info: 6: + IC(1.647 ns) + CELL(0.867 ns) = 15.156 ns; Loc. = LC_X21_Y5_N2; Fanout = 1; REG Node = 'dianzhen_out:inst2\|a\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.514 ns" { dianzhen_out:inst2|a[7]~8737 dianzhen_out:inst2|a[0] } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.256 ns ( 28.08 % ) " "Info: Total cell delay = 4.256 ns ( 28.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.900 ns ( 71.92 % ) " "Info: Total interconnect delay = 10.900 ns ( 71.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.156 ns" { boma_4 dianzhen_out:inst2|a~8680 dianzhen_out:inst2|a[7]~8727 dianzhen_out:inst2|a[7]~8729 dianzhen_out:inst2|a[7]~8737 dianzhen_out:inst2|a[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.156 ns" { boma_4 {} boma_4~out0 {} dianzhen_out:inst2|a~8680 {} dianzhen_out:inst2|a[7]~8727 {} dianzhen_out:inst2|a[7]~8729 {} dianzhen_out:inst2|a[7]~8737 {} dianzhen_out:inst2|a[0] {} } { 0.000ns 0.000ns 5.495ns 2.090ns 0.452ns 1.216ns 1.647ns } { 0.000ns 1.475ns 0.590ns 0.442ns 0.292ns 0.590ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.876 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 11.876 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianzhen.bdf" "" { Schematic "D:/altera/72/quartus/projects/dianzhen/dianzhen.bdf" { { 48 0 168 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns counter:inst\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[15\] 2 REG LC_X8_Y6_N7 4 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N7; Fanout = 4; REG Node = 'counter:inst\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[15\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] } "NODE_NAME" } } { "db/cntr_peh.tdf" "" { Text "D:/altera/72/quartus/projects/dianzhen/db/cntr_peh.tdf" 162 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.456 ns) + CELL(0.935 ns) 7.355 ns counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[2\] 3 REG LC_X9_Y6_N2 25 " "Info: 3: + IC(3.456 ns) + CELL(0.935 ns) = 7.355 ns; Loc. = LC_X9_Y6_N2; Fanout = 25; REG Node = 'counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.391 ns" { counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] } "NODE_NAME" } } { "db/cntr_peh.tdf" "" { Text "D:/altera/72/quartus/projects/dianzhen/db/cntr_peh.tdf" 162 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.810 ns) + CELL(0.711 ns) 11.876 ns dianzhen_out:inst2\|a\[0\] 4 REG LC_X21_Y5_N2 1 " "Info: 4: + IC(3.810 ns) + CELL(0.711 ns) = 11.876 ns; Loc. = LC_X21_Y5_N2; Fanout = 1; REG Node = 'dianzhen_out:inst2\|a\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.521 ns" { counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|a[0] } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 34.10 % ) " "Info: Total cell delay = 4.050 ns ( 34.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.826 ns ( 65.90 % ) " "Info: Total interconnect delay = 7.826 ns ( 65.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.876 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|a[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.876 ns" { clk {} clk~out0 {} counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] {} counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] {} dianzhen_out:inst2|a[0] {} } { 0.000ns 0.000ns 0.560ns 3.456ns 3.810ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "15.156 ns" { boma_4 dianzhen_out:inst2|a~8680 dianzhen_out:inst2|a[7]~8727 dianzhen_out:inst2|a[7]~8729 dianzhen_out:inst2|a[7]~8737 dianzhen_out:inst2|a[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "15.156 ns" { boma_4 {} boma_4~out0 {} dianzhen_out:inst2|a~8680 {} dianzhen_out:inst2|a[7]~8727 {} dianzhen_out:inst2|a[7]~8729 {} dianzhen_out:inst2|a[7]~8737 {} dianzhen_out:inst2|a[0] {} } { 0.000ns 0.000ns 5.495ns 2.090ns 0.452ns 1.216ns 1.647ns } { 0.000ns 1.475ns 0.590ns 0.442ns 0.292ns 0.590ns 0.867ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.876 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|a[0] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.876 ns" { clk {} clk~out0 {} counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] {} counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] {} dianzhen_out:inst2|a[0] {} } { 0.000ns 0.000ns 0.560ns 3.456ns 3.810ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dianzhen_4 dianzhen_out:inst2\|a\[4\] 17.178 ns register " "Info: tco from clock \"clk\" to destination pin \"dianzhen_4\" through register \"dianzhen_out:inst2\|a\[4\]\" is 17.178 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 11.876 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 11.876 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianzhen.bdf" "" { Schematic "D:/altera/72/quartus/projects/dianzhen/dianzhen.bdf" { { 48 0 168 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns counter:inst\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[15\] 2 REG LC_X8_Y6_N7 4 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N7; Fanout = 4; REG Node = 'counter:inst\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[15\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] } "NODE_NAME" } } { "db/cntr_peh.tdf" "" { Text "D:/altera/72/quartus/projects/dianzhen/db/cntr_peh.tdf" 162 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.456 ns) + CELL(0.935 ns) 7.355 ns counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[2\] 3 REG LC_X9_Y6_N2 25 " "Info: 3: + IC(3.456 ns) + CELL(0.935 ns) = 7.355 ns; Loc. = LC_X9_Y6_N2; Fanout = 25; REG Node = 'counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.391 ns" { counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] } "NODE_NAME" } } { "db/cntr_peh.tdf" "" { Text "D:/altera/72/quartus/projects/dianzhen/db/cntr_peh.tdf" 162 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.810 ns) + CELL(0.711 ns) 11.876 ns dianzhen_out:inst2\|a\[4\] 4 REG LC_X18_Y5_N7 1 " "Info: 4: + IC(3.810 ns) + CELL(0.711 ns) = 11.876 ns; Loc. = LC_X18_Y5_N7; Fanout = 1; REG Node = 'dianzhen_out:inst2\|a\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.521 ns" { counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|a[4] } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 34.10 % ) " "Info: Total cell delay = 4.050 ns ( 34.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.826 ns ( 65.90 % ) " "Info: Total interconnect delay = 7.826 ns ( 65.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.876 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|a[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.876 ns" { clk {} clk~out0 {} counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] {} counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] {} dianzhen_out:inst2|a[4] {} } { 0.000ns 0.000ns 0.560ns 3.456ns 3.810ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.078 ns + Longest register pin " "Info: + Longest register to pin delay is 5.078 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dianzhen_out:inst2\|a\[4\] 1 REG LC_X18_Y5_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y5_N7; Fanout = 1; REG Node = 'dianzhen_out:inst2\|a\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { dianzhen_out:inst2|a[4] } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.970 ns) + CELL(2.108 ns) 5.078 ns dianzhen_4 2 PIN PIN_109 0 " "Info: 2: + IC(2.970 ns) + CELL(2.108 ns) = 5.078 ns; Loc. = PIN_109; Fanout = 0; PIN Node = 'dianzhen_4'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.078 ns" { dianzhen_out:inst2|a[4] dianzhen_4 } "NODE_NAME" } } { "dianzhen.bdf" "" { Schematic "D:/altera/72/quartus/projects/dianzhen/dianzhen.bdf" { { 240 448 624 256 "dianzhen_4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 41.51 % ) " "Info: Total cell delay = 2.108 ns ( 41.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.970 ns ( 58.49 % ) " "Info: Total interconnect delay = 2.970 ns ( 58.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.078 ns" { dianzhen_out:inst2|a[4] dianzhen_4 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.078 ns" { dianzhen_out:inst2|a[4] {} dianzhen_4 {} } { 0.000ns 2.970ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.876 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|a[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.876 ns" { clk {} clk~out0 {} counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] {} counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] {} dianzhen_out:inst2|a[4] {} } { 0.000ns 0.000ns 0.560ns 3.456ns 3.810ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.078 ns" { dianzhen_out:inst2|a[4] dianzhen_4 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.078 ns" { dianzhen_out:inst2|a[4] {} dianzhen_4 {} } { 0.000ns 2.970ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "dianzhen_out:inst2\|counter1\[7\] boma_4 clk 4.046 ns register " "Info: th for register \"dianzhen_out:inst2\|counter1\[7\]\" (data pin = \"boma_4\", clock pin = \"clk\") is 4.046 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.914 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 11.914 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianzhen.bdf" "" { Schematic "D:/altera/72/quartus/projects/dianzhen/dianzhen.bdf" { { 48 0 168 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.935 ns) 2.964 ns counter:inst\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[15\] 2 REG LC_X8_Y6_N7 4 " "Info: 2: + IC(0.560 ns) + CELL(0.935 ns) = 2.964 ns; Loc. = LC_X8_Y6_N7; Fanout = 4; REG Node = 'counter:inst\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[15\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] } "NODE_NAME" } } { "db/cntr_peh.tdf" "" { Text "D:/altera/72/quartus/projects/dianzhen/db/cntr_peh.tdf" 162 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.456 ns) + CELL(0.935 ns) 7.355 ns counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[2\] 3 REG LC_X9_Y6_N2 25 " "Info: 3: + IC(3.456 ns) + CELL(0.935 ns) = 7.355 ns; Loc. = LC_X9_Y6_N2; Fanout = 25; REG Node = 'counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.391 ns" { counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] } "NODE_NAME" } } { "db/cntr_peh.tdf" "" { Text "D:/altera/72/quartus/projects/dianzhen/db/cntr_peh.tdf" 162 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.848 ns) + CELL(0.711 ns) 11.914 ns dianzhen_out:inst2\|counter1\[7\] 4 REG LC_X20_Y8_N0 2 " "Info: 4: + IC(3.848 ns) + CELL(0.711 ns) = 11.914 ns; Loc. = LC_X20_Y8_N0; Fanout = 2; REG Node = 'dianzhen_out:inst2\|counter1\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.559 ns" { counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|counter1[7] } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 33.99 % ) " "Info: Total cell delay = 4.050 ns ( 33.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.864 ns ( 66.01 % ) " "Info: Total interconnect delay = 7.864 ns ( 66.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.914 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|counter1[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.914 ns" { clk {} clk~out0 {} counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] {} counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] {} dianzhen_out:inst2|counter1[7] {} } { 0.000ns 0.000ns 0.560ns 3.456ns 3.848ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.883 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.883 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns boma_4 1 PIN PIN_121 17 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_121; Fanout = 17; PIN Node = 'boma_4'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { boma_4 } "NODE_NAME" } } { "dianzhen.bdf" "" { Schematic "D:/altera/72/quartus/projects/dianzhen/dianzhen.bdf" { { 184 -16 152 200 "boma_4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.541 ns) + CELL(0.867 ns) 7.883 ns dianzhen_out:inst2\|counter1\[7\] 2 REG LC_X20_Y8_N0 2 " "Info: 2: + IC(5.541 ns) + CELL(0.867 ns) = 7.883 ns; Loc. = LC_X20_Y8_N0; Fanout = 2; REG Node = 'dianzhen_out:inst2\|counter1\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.408 ns" { boma_4 dianzhen_out:inst2|counter1[7] } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.342 ns ( 29.71 % ) " "Info: Total cell delay = 2.342 ns ( 29.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.541 ns ( 70.29 % ) " "Info: Total interconnect delay = 5.541 ns ( 70.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.883 ns" { boma_4 dianzhen_out:inst2|counter1[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.883 ns" { boma_4 {} boma_4~out0 {} dianzhen_out:inst2|counter1[7] {} } { 0.000ns 0.000ns 5.541ns } { 0.000ns 1.475ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.914 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|counter1[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.914 ns" { clk {} clk~out0 {} counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] {} counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] {} dianzhen_out:inst2|counter1[7] {} } { 0.000ns 0.000ns 0.560ns 3.456ns 3.848ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.883 ns" { boma_4 dianzhen_out:inst2|counter1[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.883 ns" { boma_4 {} boma_4~out0 {} dianzhen_out:inst2|counter1[7] {} } { 0.000ns 0.000ns 5.541ns } { 0.000ns 1.475ns 0.867ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}