dianzhen_out.v.bak

来自「基于FPGA的8*8点阵控制」· BAK 代码 · 共 156 行

module dianzhen_out(clk,a,en);
input clk,en;
output reg [7:0]a;
reg [15:0]counter1;

always@(posedge clk)
  begin
  if(!en)
  begin
  counter1=counter1+1;
    if(counter1==1)
       a<=8'b00000001;
    if(counter1==10)
       a<=8'b00000010;
    if(counter1==20)
       a<=8'b00000100;
    if(counter1==30)
       a<=8'b00001000;
    if(counter1==40)
       a<=8'b00010000;
    if(counter1==50)
       a<=8'b00100000;
    if(counter1==60)
       a<=8'b01000000;
    if(counter1==70)
       a<=8'b10000000;
    if(counter1==80)
       a<=8'b10000001;
    if(counter1==90)
       a<=8'b10000010;
    if(counter1==100)
       a<=8'b10000100;
    if(counter1==110)
       a<=8'b10001000;
    if(counter1==120)
       a<=8'b10010000;
    if(counter1==130)
       a<=8'b10100000;
    if(counter1==140)
       a<=8'b11000000;
    if(counter1==150)
       a<=8'b11000001;
    if(counter1==160)
       a<=8'b11000010;
    if(counter1==170)
       a<=8'b11000100;
    if(counter1==180)
       a<=8'b11001000;
    if(counter1==190)
       a<=8'b11010000;
    if(counter1==200)
       a<=8'b11100000;
    if(counter1==210)
       a<=8'b11100001;
    if(counter1==220)
       a<=8'b11100010;
    if(counter1==230)
       a<=8'b11100100;
    if(counter1==240)
       a<=8'b11101000;
    if(counter1==250)
       a<=8'b11110000;
    if(counter1==260)
       a<=8'b11110001;
    if(counter1==270)
       a<=8'b11110010;
    if(counter1==290)
       a<=8'b11110100;
    if(counter1==310)
       a<=8'b11111000;
    if(counter1==330)
       a<=8'b11111001;
    if(counter1==350)
       a<=8'b11111010;
    if(counter1==370)
       a<=8'b11111100;
    if(counter1==380)
       a<=8'b11111101;   
    if(counter1==390)
       a<=8'b11111110;    
    if(counter1==400)
       a<=8'b11111111;
    if(counter1==450)
       a<=8'b11111100;
    if(counter1==460)
       a<=8'b11110011;
    if(counter1==470)
       a<=8'b11110000;
    if(counter1==480)
       a<=8'b11001100;
    if(counter1==490)
       a<=8'b11000011;
    if(counter1==500)
       a<=8'b11000000;
    if(counter1==510)
       a<=8'b00110000;
    if(counter1==520)
       a<=8'b00001100;
    if(counter1==530)
       a<=8'b00000011;
    if(counter1==540)
       a<=8'b00000000;
    if(counter1==550)
       a<=8'b10000001;
    if(counter1==560)
       a<=8'b11000011;
    if(counter1==570)
       a<=8'b11100111;
    if(counter1==580)
       a<=8'b11111111;
    if(counter1==590)
       a<=8'b01111110;
    if(counter1==600)
       a<=8'b00111100;
    if(counter1==610)
       a<=8'b00011000;
    if(counter1==640)
       a<=8'b00100100;
    if(counter1==650)
       a<=8'b01000010;
    if(counter1==660)
       a<=8'b10000001;
    if(counter1==670)
       a<=8'b00000000;
    if(counter1==680)
       a<=8'b11111111;
    if(counter1==720)
       a<=8'b00000000;
    
    if(counter1==750)
       a<=8'b11110000;
    if(counter1==780)
       a<=8'b00001111;
    if(counter1==810)
       a<=8'b11110000;
    
    if(counter1==830)
       a<=8'b00000000;
    if(counter1==850)
       a<=8'b01010101;
    if(counter1==900)
       a<=8'b10101010;
    
    if(counter1==1000)
    begin       
       counter1<=0;
       a<=8'b00000000;
    end
end
else
    begin
    a<=8'b00000000;
    end
end
endmodule