dianzhen.v

来自「基于FPGA的8*8点阵控制」· Verilog 代码 · 共 20 行

module dianzhen_out(clk,a);
input clk;
output [7:0]a;
reg [15:0]counter;

always @(posedge clk)
  begin
  counter=counter+1;
    if(counter==1)
       a<=8'b00000001;
    if(counter==10)
       a<=8'b00000010;
    if(counter==20)
       
       counter<=0;
       a<=8'b00000000;
 
   end
endmodule