prev_cmp_dianzhen.tan.qmsg

基于FPGA的8*8点阵控制

{ "Info" "ITDB_TSU_RESULT" "dianzhen_out:inst2\|a\[2\] boma_4 clk 1.642 ns register " "Info: tsu for register \"dianzhen_out:inst2\|a\[2\]\" (data pin = \"boma_4\", clock pin = \"clk\") is 1.642 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.679 ns + Longest pin register " "Info: + Longest pin to register delay is 13.679 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns boma_4 1 PIN PIN_121 18 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_121; Fanout = 18; PIN Node = 'boma_4'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { boma_4 } "NODE_NAME" } } { "dianzhen.bdf" "" { Schematic "D:/altera/72/quartus/projects/dianzhen/dianzhen.bdf" { { 184 -16 152 200 "boma_4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.235 ns) + CELL(0.590 ns) 8.300 ns dianzhen_out:inst2\|a~6077 2 COMB LC_X15_Y8_N0 6 " "Info: 2: + IC(6.235 ns) + CELL(0.590 ns) = 8.300 ns; Loc. = LC_X15_Y8_N0; Fanout = 6; COMB Node = 'dianzhen_out:inst2\|a~6077'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.825 ns" { boma_4 dianzhen_out:inst2|a~6077 } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.265 ns) + CELL(0.114 ns) 9.679 ns dianzhen_out:inst2\|a\[7\]~6078 3 COMB LC_X16_Y5_N1 1 " "Info: 3: + IC(1.265 ns) + CELL(0.114 ns) = 9.679 ns; Loc. = LC_X16_Y5_N1; Fanout = 1; COMB Node = 'dianzhen_out:inst2\|a\[7\]~6078'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.379 ns" { dianzhen_out:inst2|a~6077 dianzhen_out:inst2|a[7]~6078 } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.564 ns) + CELL(0.292 ns) 11.535 ns dianzhen_out:inst2\|a\[7\]~6080 4 COMB LC_X18_Y6_N8 8 " "Info: 4: + IC(1.564 ns) + CELL(0.292 ns) = 11.535 ns; Loc. = LC_X18_Y6_N8; Fanout = 8; COMB Node = 'dianzhen_out:inst2\|a\[7\]~6080'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.856 ns" { dianzhen_out:inst2|a[7]~6078 dianzhen_out:inst2|a[7]~6080 } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.277 ns) + CELL(0.867 ns) 13.679 ns dianzhen_out:inst2\|a\[2\] 5 REG LC_X19_Y8_N9 1 " "Info: 5: + IC(1.277 ns) + CELL(0.867 ns) = 13.679 ns; Loc. = LC_X19_Y8_N9; Fanout = 1; REG Node = 'dianzhen_out:inst2\|a\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.144 ns" { dianzhen_out:inst2|a[7]~6080 dianzhen_out:inst2|a[2] } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.338 ns ( 24.40 % ) " "Info: Total cell delay = 3.338 ns ( 24.40 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.341 ns ( 75.60 % ) " "Info: Total interconnect delay = 10.341 ns ( 75.60 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.679 ns" { boma_4 dianzhen_out:inst2|a~6077 dianzhen_out:inst2|a[7]~6078 dianzhen_out:inst2|a[7]~6080 dianzhen_out:inst2|a[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.679 ns" { boma_4 {} boma_4~out0 {} dianzhen_out:inst2|a~6077 {} dianzhen_out:inst2|a[7]~6078 {} dianzhen_out:inst2|a[7]~6080 {} dianzhen_out:inst2|a[2] {} } { 0.000ns 0.000ns 6.235ns 1.265ns 1.564ns 1.277ns } { 0.000ns 1.475ns 0.590ns 0.114ns 0.292ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.074 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 12.074 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianzhen.bdf" "" { Schematic "D:/altera/72/quartus/projects/dianzhen/dianzhen.bdf" { { 48 0 168 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns counter:inst\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[15\] 2 REG LC_X7_Y4_N7 4 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y4_N7; Fanout = 4; REG Node = 'counter:inst\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[15\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] } "NODE_NAME" } } { "db/cntr_peh.tdf" "" { Text "D:/altera/72/quartus/projects/dianzhen/db/cntr_peh.tdf" 162 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.975 ns) + CELL(0.935 ns) 7.864 ns counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[2\] 3 REG LC_X8_Y6_N2 25 " "Info: 3: + IC(3.975 ns) + CELL(0.935 ns) = 7.864 ns; Loc. = LC_X8_Y6_N2; Fanout = 25; REG Node = 'counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.910 ns" { counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] } "NODE_NAME" } } { "db/cntr_peh.tdf" "" { Text "D:/altera/72/quartus/projects/dianzhen/db/cntr_peh.tdf" 162 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 12.074 ns dianzhen_out:inst2\|a\[2\] 4 REG LC_X19_Y8_N9 1 " "Info: 4: + IC(3.499 ns) + CELL(0.711 ns) = 12.074 ns; Loc. = LC_X19_Y8_N9; Fanout = 1; REG Node = 'dianzhen_out:inst2\|a\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.210 ns" { counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|a[2] } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 33.54 % ) " "Info: Total cell delay = 4.050 ns ( 33.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.024 ns ( 66.46 % ) " "Info: Total interconnect delay = 8.024 ns ( 66.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.074 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|a[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.074 ns" { clk {} clk~out0 {} counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] {} counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] {} dianzhen_out:inst2|a[2] {} } { 0.000ns 0.000ns 0.550ns 3.975ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "13.679 ns" { boma_4 dianzhen_out:inst2|a~6077 dianzhen_out:inst2|a[7]~6078 dianzhen_out:inst2|a[7]~6080 dianzhen_out:inst2|a[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "13.679 ns" { boma_4 {} boma_4~out0 {} dianzhen_out:inst2|a~6077 {} dianzhen_out:inst2|a[7]~6078 {} dianzhen_out:inst2|a[7]~6080 {} dianzhen_out:inst2|a[2] {} } { 0.000ns 0.000ns 6.235ns 1.265ns 1.564ns 1.277ns } { 0.000ns 1.475ns 0.590ns 0.114ns 0.292ns 0.867ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.074 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|a[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.074 ns" { clk {} clk~out0 {} counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] {} counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] {} dianzhen_out:inst2|a[2] {} } { 0.000ns 0.000ns 0.550ns 3.975ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dianzhen_1 dianzhen_out:inst2\|a\[7\] 16.942 ns register " "Info: tco from clock \"clk\" to destination pin \"dianzhen_1\" through register \"dianzhen_out:inst2\|a\[7\]\" is 16.942 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.074 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 12.074 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianzhen.bdf" "" { Schematic "D:/altera/72/quartus/projects/dianzhen/dianzhen.bdf" { { 48 0 168 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns counter:inst\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[15\] 2 REG LC_X7_Y4_N7 4 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y4_N7; Fanout = 4; REG Node = 'counter:inst\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[15\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] } "NODE_NAME" } } { "db/cntr_peh.tdf" "" { Text "D:/altera/72/quartus/projects/dianzhen/db/cntr_peh.tdf" 162 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.975 ns) + CELL(0.935 ns) 7.864 ns counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[2\] 3 REG LC_X8_Y6_N2 25 " "Info: 3: + IC(3.975 ns) + CELL(0.935 ns) = 7.864 ns; Loc. = LC_X8_Y6_N2; Fanout = 25; REG Node = 'counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.910 ns" { counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] } "NODE_NAME" } } { "db/cntr_peh.tdf" "" { Text "D:/altera/72/quartus/projects/dianzhen/db/cntr_peh.tdf" 162 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 12.074 ns dianzhen_out:inst2\|a\[7\] 4 REG LC_X18_Y6_N9 1 " "Info: 4: + IC(3.499 ns) + CELL(0.711 ns) = 12.074 ns; Loc. = LC_X18_Y6_N9; Fanout = 1; REG Node = 'dianzhen_out:inst2\|a\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.210 ns" { counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|a[7] } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 33.54 % ) " "Info: Total cell delay = 4.050 ns ( 33.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.024 ns ( 66.46 % ) " "Info: Total interconnect delay = 8.024 ns ( 66.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.074 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|a[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.074 ns" { clk {} clk~out0 {} counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] {} counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] {} dianzhen_out:inst2|a[7] {} } { 0.000ns 0.000ns 0.550ns 3.975ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.644 ns + Longest register pin " "Info: + Longest register to pin delay is 4.644 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dianzhen_out:inst2\|a\[7\] 1 REG LC_X18_Y6_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X18_Y6_N9; Fanout = 1; REG Node = 'dianzhen_out:inst2\|a\[7\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { dianzhen_out:inst2|a[7] } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.536 ns) + CELL(2.108 ns) 4.644 ns dianzhen_1 2 PIN PIN_120 0 " "Info: 2: + IC(2.536 ns) + CELL(2.108 ns) = 4.644 ns; Loc. = PIN_120; Fanout = 0; PIN Node = 'dianzhen_1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.644 ns" { dianzhen_out:inst2|a[7] dianzhen_1 } "NODE_NAME" } } { "dianzhen.bdf" "" { Schematic "D:/altera/72/quartus/projects/dianzhen/dianzhen.bdf" { { 168 448 624 184 "dianzhen_1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 45.39 % ) " "Info: Total cell delay = 2.108 ns ( 45.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.536 ns ( 54.61 % ) " "Info: Total interconnect delay = 2.536 ns ( 54.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.644 ns" { dianzhen_out:inst2|a[7] dianzhen_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.644 ns" { dianzhen_out:inst2|a[7] {} dianzhen_1 {} } { 0.000ns 2.536ns } { 0.000ns 2.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.074 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|a[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.074 ns" { clk {} clk~out0 {} counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] {} counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] {} dianzhen_out:inst2|a[7] {} } { 0.000ns 0.000ns 0.550ns 3.975ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.644 ns" { dianzhen_out:inst2|a[7] dianzhen_1 } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.644 ns" { dianzhen_out:inst2|a[7] {} dianzhen_1 {} } { 0.000ns 2.536ns } { 0.000ns 2.108ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "dianzhen_out:inst2\|counter1\[2\] boma_4 clk 3.461 ns register " "Info: th for register \"dianzhen_out:inst2\|counter1\[2\]\" (data pin = \"boma_4\", clock pin = \"clk\") is 3.461 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.074 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 12.074 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_16 16 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_16; Fanout = 16; CLK Node = 'clk'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianzhen.bdf" "" { Schematic "D:/altera/72/quartus/projects/dianzhen/dianzhen.bdf" { { 48 0 168 64 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.550 ns) + CELL(0.935 ns) 2.954 ns counter:inst\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[15\] 2 REG LC_X7_Y4_N7 4 " "Info: 2: + IC(0.550 ns) + CELL(0.935 ns) = 2.954 ns; Loc. = LC_X7_Y4_N7; Fanout = 4; REG Node = 'counter:inst\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[15\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] } "NODE_NAME" } } { "db/cntr_peh.tdf" "" { Text "D:/altera/72/quartus/projects/dianzhen/db/cntr_peh.tdf" 162 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.975 ns) + CELL(0.935 ns) 7.864 ns counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[2\] 3 REG LC_X8_Y6_N2 25 " "Info: 3: + IC(3.975 ns) + CELL(0.935 ns) = 7.864 ns; Loc. = LC_X8_Y6_N2; Fanout = 25; REG Node = 'counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.910 ns" { counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] } "NODE_NAME" } } { "db/cntr_peh.tdf" "" { Text "D:/altera/72/quartus/projects/dianzhen/db/cntr_peh.tdf" 162 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.499 ns) + CELL(0.711 ns) 12.074 ns dianzhen_out:inst2\|counter1\[2\] 4 REG LC_X15_Y8_N6 2 " "Info: 4: + IC(3.499 ns) + CELL(0.711 ns) = 12.074 ns; Loc. = LC_X15_Y8_N6; Fanout = 2; REG Node = 'dianzhen_out:inst2\|counter1\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.210 ns" { counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|counter1[2] } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 33.54 % ) " "Info: Total cell delay = 4.050 ns ( 33.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.024 ns ( 66.46 % ) " "Info: Total interconnect delay = 8.024 ns ( 66.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.074 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|counter1[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.074 ns" { clk {} clk~out0 {} counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] {} counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] {} dianzhen_out:inst2|counter1[2] {} } { 0.000ns 0.000ns 0.550ns 3.975ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.628 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.628 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.475 ns) 1.475 ns boma_4 1 PIN PIN_121 18 " "Info: 1: + IC(0.000 ns) + CELL(1.475 ns) = 1.475 ns; Loc. = PIN_121; Fanout = 18; PIN Node = 'boma_4'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { boma_4 } "NODE_NAME" } } { "dianzhen.bdf" "" { Schematic "D:/altera/72/quartus/projects/dianzhen/dianzhen.bdf" { { 184 -16 152 200 "boma_4" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.286 ns) + CELL(0.867 ns) 8.628 ns dianzhen_out:inst2\|counter1\[2\] 2 REG LC_X15_Y8_N6 2 " "Info: 2: + IC(6.286 ns) + CELL(0.867 ns) = 8.628 ns; Loc. = LC_X15_Y8_N6; Fanout = 2; REG Node = 'dianzhen_out:inst2\|counter1\[2\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.153 ns" { boma_4 dianzhen_out:inst2|counter1[2] } "NODE_NAME" } } { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.342 ns ( 27.14 % ) " "Info: Total cell delay = 2.342 ns ( 27.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.286 ns ( 72.86 % ) " "Info: Total interconnect delay = 6.286 ns ( 72.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.628 ns" { boma_4 dianzhen_out:inst2|counter1[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.628 ns" { boma_4 {} boma_4~out0 {} dianzhen_out:inst2|counter1[2] {} } { 0.000ns 0.000ns 6.286ns } { 0.000ns 1.475ns 0.867ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.074 ns" { clk counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] dianzhen_out:inst2|counter1[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.074 ns" { clk {} clk~out0 {} counter:inst|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[15] {} counter:inst1|lpm_counter:lpm_counter_component|cntr_peh:auto_generated|safe_q[2] {} dianzhen_out:inst2|counter1[2] {} } { 0.000ns 0.000ns 0.550ns 3.975ns 3.499ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.628 ns" { boma_4 dianzhen_out:inst2|counter1[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.628 ns" { boma_4 {} boma_4~out0 {} dianzhen_out:inst2|counter1[2] {} } { 0.000ns 0.000ns 6.286ns } { 0.000ns 1.475ns 0.867ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}