prev_cmp_dianzhen.map.qmsg

基于FPGA的8*8点阵控制

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Mar 14 01:37:23 2008 " "Info: Processing started: Fri Mar 14 01:37:23 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dianzhen -c dianzhen " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dianzhen -c dianzhen" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dianzhen.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file dianzhen.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 dianzhen " "Info: Found entity 1: dianzhen" {  } { { "dianzhen.bdf" "" { Schematic "D:/altera/72/quartus/projects/dianzhen/dianzhen.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dianzhen_out.v(6) " "Warning (10268): Verilog HDL information at dianzhen_out.v(6): Always Construct contains both blocking and non-blocking assignments" {  } { { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 6 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dianzhen_out.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dianzhen_out.v" { { "Info" "ISGN_ENTITY_NAME" "1 dianzhen_out " "Info: Found entity 1: dianzhen_out" {  } { { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dianzhen " "Info: Elaborating entity \"dianzhen\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dianzhen_out dianzhen_out:inst2 " "Info: Elaborating entity \"dianzhen_out\" for hierarchy \"dianzhen_out:inst2\"" {  } { { "dianzhen.bdf" "inst2" { Schematic "D:/altera/72/quartus/projects/dianzhen/dianzhen.bdf" { { 144 208 304 240 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 dianzhen_out.v(10) " "Warning (10230): Verilog HDL assignment warning at dianzhen_out.v(10): truncated value with size 32 to match size of target (16)" {  } { { "dianzhen_out.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/dianzhen_out.v" 10 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "counter.v 1 1 " "Warning: Using design file counter.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 counter " "Info: Found entity 1: counter" {  } { { "counter.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/counter.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Warning" "WSGN_SKIP_FILE_CANDID_TOP" "counter " "Warning (12300): Found the following files while searching for definition of entity \"counter\", but did not use these files because already using a different file containing the entity definition" { { "Warning" "WSGN_SKIP_FILE_CANDID_SUB" "counter.vhd " "Warning: File: counter.vhd" {  } {  } 0 0 "File: %1!s!" 0 0 "" 0}  } {  } 0 12300 "Found the following files while searching for definition of entity \"%1!s!\", but did not use these files because already using a different file containing the entity definition" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "counter counter:inst1 " "Info: Elaborating entity \"counter\" for hierarchy \"counter:inst1\"" {  } { { "dianzhen.bdf" "inst1" { Schematic "D:/altera/72/quartus/projects/dianzhen/dianzhen.bdf" { { 24 472 616 88 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 248 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter counter:inst1\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"counter:inst1\|lpm_counter:lpm_counter_component\"" {  } { { "counter.v" "lpm_counter_component" { Text "D:/altera/72/quartus/projects/dianzhen/counter.v" 64 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "counter:inst1\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"counter:inst1\|lpm_counter:lpm_counter_component\"" {  } { { "counter.v" "" { Text "D:/altera/72/quartus/projects/dianzhen/counter.v" 64 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_peh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_peh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_peh " "Info: Found entity 1: cntr_peh" {  } { { "db/cntr_peh.tdf" "" { Text "D:/altera/72/quartus/projects/dianzhen/db/cntr_peh.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_peh counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated " "Info: Elaborating entity \"cntr_peh\" for hierarchy \"counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "d:/altera/72/quartus/libraries/megafunctions/lpm_counter.tdf" 272 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "13 13 " "Info: 13 registers lost all their fanouts during netlist optimizations. The first 13 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[3\] " "Info: Register \"counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[3\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[4\] " "Info: Register \"counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[4\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[5\] " "Info: Register \"counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[5\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[6\] " "Info: Register \"counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[6\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[7\] " "Info: Register \"counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[7\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[8\] " "Info: Register \"counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[8\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[9\] " "Info: Register \"counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[9\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[10\] " "Info: Register \"counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[10\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[11\] " "Info: Register \"counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[11\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[12\] " "Info: Register \"counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[12\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[13\] " "Info: Register \"counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[13\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[14\] " "Info: Register \"counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[14\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[15\] " "Info: Register \"counter:inst1\|lpm_counter:lpm_counter_component\|cntr_peh:auto_generated\|safe_q\[15\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/altera/72/quartus/projects/dianzhen/dianzhen.map.smsg " "Info: Generated suppressed messages file D:/altera/72/quartus/projects/dianzhen/dianzhen.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "294 " "Info: Implemented 294 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "284 " "Info: Implemented 284 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "148 " "Info: Allocated 148 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 14 01:37:36 2008 " "Info: Processing ended: Fri Mar 14 01:37:36 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}