dianzhen.tan.summary

基于FPGA的8*8点阵控制

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 3.317 ns
From           : boma_4
To             : dianzhen_out:inst2|a[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 17.178 ns
From           : dianzhen_out:inst2|a[4]
To             : dianzhen_4
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 4.046 ns
From           : boma_4
To             : dianzhen_out:inst2|counter1[3]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 61.21 MHz ( period = 16.336 ns )
From           : dianzhen_out:inst2|counter1[8]
To             : dianzhen_out:inst2|a[2]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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