sine64.tan.rpt

chdl 64位计数器

; N/A   ; None         ; 7.764 ns   ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5] ; q[5] ; clk        ;
; N/A   ; None         ; 7.760 ns   ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[4] ; q[4] ; clk        ;
; N/A   ; None         ; 7.756 ns   ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7] ; q[7] ; clk        ;
; N/A   ; None         ; 7.752 ns   ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[6] ; q[6] ; clk        ;
; N/A   ; None         ; 7.459 ns   ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[2] ; q[2] ; clk        ;
; N/A   ; None         ; 7.451 ns   ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[3] ; q[3] ; clk        ;
; N/A   ; None         ; 7.180 ns   ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[0] ; q[0] ; clk        ;
; N/A   ; None         ; 7.148 ns   ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[1] ; q[1] ; clk        ;
+-------+--------------+------------+-----------------------------------------------------------------------------------+------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Sat Mar 24 15:25:35 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off sine64 -c sine64 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 197.01 MHz between source memory "rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0" and destination memory "rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7]" (period= 5.076 ns)
    Info: + Longest memory to memory delay is 4.319 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y1; Fanout = 8; MEM Node = 'rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X13_Y1; Fanout = 1; MEM Node = 'rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7]'
        Info: Total cell delay = 4.319 ns ( 100.00 % )
    Info: - Smallest clock skew is -0.014 ns
        Info: + Shortest clock path from clock "clk" to destination memory is 2.740 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 21; CLK Node = 'clk'
            Info: 2: + IC(0.563 ns) + CELL(0.708 ns) = 2.740 ns; Loc. = M4K_X13_Y1; Fanout = 1; MEM Node = 'rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7]'
            Info: Total cell delay = 2.177 ns ( 79.45 % )
            Info: Total interconnect delay = 0.563 ns ( 20.55 % )
        Info: - Longest clock path from clock "clk" to source memory is 2.754 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 21; CLK Node = 'clk'
            Info: 2: + IC(0.563 ns) + CELL(0.722 ns) = 2.754 ns; Loc. = M4K_X13_Y1; Fanout = 8; MEM Node = 'rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0'
            Info: Total cell delay = 2.191 ns ( 79.56 % )
            Info: Total interconnect delay = 0.563 ns ( 20.44 % )
    Info: + Micro clock to output delay of source is 0.650 ns
    Info: + Micro setup delay of destination is 0.093 ns
Info: tco from clock "clk" to destination pin "q[5]" through memory "rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5]" is 7.764 ns
    Info: + Longest clock path from clock "clk" to source memory is 2.740 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_93; Fanout = 21; CLK Node = 'clk'
        Info: 2: + IC(0.563 ns) + CELL(0.708 ns) = 2.740 ns; Loc. = M4K_X13_Y1; Fanout = 1; MEM Node = 'rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5]'
        Info: Total cell delay = 2.177 ns ( 79.45 % )
        Info: Total interconnect delay = 0.563 ns ( 20.55 % )
    Info: + Micro clock to output delay of source is 0.650 ns
    Info: + Longest memory to pin delay is 4.374 ns
        Info: 1: + IC(0.000 ns) + CELL(0.104 ns) = 0.104 ns; Loc. = M4K_X13_Y1; Fanout = 1; MEM Node = 'rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[5]'
        Info: 2: + IC(2.162 ns) + CELL(2.108 ns) = 4.374 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'q[5]'
        Info: Total cell delay = 2.212 ns ( 50.57 % )
        Info: Total interconnect delay = 2.162 ns ( 49.43 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Mar 24 15:25:35 2007
    Info: Elapsed time: 00:00:01