sine64.tan.rpt

来自「chdl 64位计数器」· RPT 代码 · 共 234 行 · 第 1/4 页

; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                                                                           ;
+-------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From                                                                                                       ; To                                                                                                         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg1 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg2 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg3 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg4 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg5 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[7]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg1 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg2 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg3 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg4 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg5 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[0]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[1]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg1 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[1]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg2 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[1]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg3 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[1]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg4 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[1]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg5 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[1]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[2]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg1 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[2]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg2 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[2]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg3 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[2]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg4 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[2]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg5 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[2]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg0 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[3]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg1 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[3]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg2 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[3]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg3 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[3]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg4 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[3]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;
; N/A   ; 197.01 MHz ( period = 5.076 ns )               ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|ram_block1a7~porta_address_reg5 ; rom64:inst1|altsyncram:altsyncram_component|altsyncram_8v21:auto_generated|q_a[3]                          ; clk        ; clk      ; None                        ; None                      ; 4.319 ns                ;