add.v

使用verilog作为CPU设计语言实现单数据通路五级流水线的CPU。具有32个通用寄存器、一个程序计数器PC、一个标志寄存器FLAG

module add (opa,opb,out);
input [31:0]opa,opb;
output[31:0]out;

wire [31:0]opa,opb;
wire [31:0]out;

wire sign;
wire [7:0]expout;
wire [22:0]tail23;
wire [23:0]tail24;

wire sign_1;                 //case 1
wire [7:0]expout_1;
wire [22:0]tail23_1;
wire [23:0]tail24_1;


wire sign_2;               //case 2
wire [7:0]expout_2;
wire [22:0]tail23_2;
wire [23:0]tail24_2;


wire [7:0]expa;
wire [7:0]expb;
wire signa;
wire signb;
wire [22:0]a23;
wire [23:0]a24;
wire [22:0]b23;
wire [23:0]b24;

wire [7:0]shifta_1;
wire [7:0]shiftb_1;
wire [7:0]shifta_2;
wire [7:0]shiftb_2;

assign expa=opa[30:23];
assign expb=opb[30:23];
assign signa=opa[31];
assign signb=opb[31];
assign a23=opa[22:0];
assign b23=opb[22:0];
assign a24={1'b1,a23};
assign b24={1'b1,b23};

///////////////////////////////////////////////////
//case 1同号
//
assign sign_1=signa;

assign shifta_1= expb>=expa?1+expb-expa:1;
assign shiftb_1= expa>=expb?1+expa-expb:1;

assign expout_1=expb>=expa?expb:expa;//取大的指数
                                     // 别忘了return的case

wire [23:0]temp_tail_1;
assign temp_tail_1=(a24>>shifta_1)+(b24>>shiftb_1); //小树部分
                    //各自至少移动了一位，故加起来最多24位
wire [7:0]expout_final_1;
wire [22:0]temp_tail_final_1;
assign expout_final_1=temp_tail_1[23]==1?expout_1+1:expout_1;//有进位指数加1

assign temp_tail_final_1=(temp_tail_1[23]==1)?temp_tail_1[22:0]:{temp_tail_1[21:0],1'b0};

															//有进位 去1个头部，没则去两个头部
wire [31:0]case_1_out;
assign case_1_out={sign_1,expout_final_1,temp_tail_final_1};

////////////////////////////////////////////////////////////////															
//case 2 不同号


assign shifta_2= expb>=expa?expb-expa:0; //移位
assign shiftb_2= expa>=expb?expa-expb:0;

assign expout_2=expb>=expa?expb:expa;//取大的指数
                                     // 别忘了return的case

wire a_lt_b;
assign a_lt_b=opa[30:0]>=opb[30:0];//判断绝对值得大小
                                   //相减综合
wire [23:0]temp_tail_2;
assign temp_tail_2=a_lt_b?
	((a24>>shifta_2)-(b24>>shiftb_2)):((b24>>shiftb_2)-(a24>>shifta_2)); //小数部分
                    //各自至少移动了一位，故加起来最多24位
wire [7:0]expout_final_2;
wire [22:0]temp_tail_final_2;

//浮点移动
reg [4:0]float;
always @(temp_tail_2)
	casex(temp_tail_2[22:0])                       //观察其小数位
	   23'b1??????????????????????: float = 0;
	   23'b01?????????????????????: float = 1;
	   23'b001????????????????????: float = 2;
	   23'b0001???????????????????: float = 3;
	   23'b00001??????????????????: float = 4;
	   23'b000001?????????????????: float = 5;
	   23'b0000001????????????????: float = 6;
	   23'b00000001???????????????: float = 7;
	   23'b000000001??????????????: float = 8;
	   23'b0000000001?????????????: float = 9;
	   23'b00000000001????????????: float = 10;
	   23'b000000000001???????????: float = 11;
	   23'b0000000000001??????????: float = 12;
	   23'b00000000000001?????????: float = 13;
	   23'b000000000000001????????: float = 14;
	   23'b0000000000000001???????: float = 15;
	   23'b00000000000000001??????: float = 16;
	   23'b000000000000000001?????: float = 17;
	   23'b0000000000000000001????: float = 18;
	   23'b00000000000000000001???: float = 19;
	   23'b000000000000000000001??: float = 20;
	   23'b0000000000000000000001?: float = 21;
	   23'b0000000000000000000000?: float = 22;
	endcase
	
assign expout_final_2=expout_2-(float+1);	
assign sign_2=a_lt_b?signa:signb;
assign temp_tail_final_2=temp_tail_2<<(float+1);//temp_tail_2 是24 bit 移动float+1
wire [31:0]case_2_out;

assign case_2_out={sign_2,expout_final_2,temp_tail_final_2};

assign out=signa^signb?case_2_out:case_1_out;

endmodule