📄 ss_syn.v
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.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_4.connectivity_checking = "OFF",
ram_block1a_4.init_file = "instruction_mem.mif",
ram_block1a_4.init_file_layout = "port_a",
ram_block1a_4.logical_ram_name = "ALTSYNCRAM",
ram_block1a_4.mem_init0 = 256'h8000000000000000000000000000000000000000000000000000000000000018,
ram_block1a_4.operation_mode = "single_port",
ram_block1a_4.port_a_address_width = 8,
ram_block1a_4.port_a_data_out_clear = "none",
ram_block1a_4.port_a_data_out_clock = "clock0",
ram_block1a_4.port_a_data_width = 1,
ram_block1a_4.port_a_disable_ce_on_input_registers = "off",
ram_block1a_4.port_a_disable_ce_on_output_registers = "off",
ram_block1a_4.port_a_first_address = 0,
ram_block1a_4.port_a_first_bit_number = 4,
ram_block1a_4.port_a_last_address = 255,
ram_block1a_4.port_a_logical_ram_depth = 256,
ram_block1a_4.port_a_logical_ram_width = 8,
ram_block1a_4.power_up_uninitialized = "false",
ram_block1a_4.ram_block_type = "AUTO",
ram_block1a_4.lpm_type = "cycloneii_ram_block",
ram_block1a_4.lpm_hint = "DONT_POWER_OPTIMIZE=ON";
cycloneii_ram_block ram_block1a_5
(
.clk0(clock0),
.ena0(clocken0),
.portaaddr({address_a_wire[7:0]}),
.portadatain({data_a[5]}),
.portadataout(wire_ram_block1a_5portadataout[0:0]),
.portawe(wren_a),
.portbdataout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_5.connectivity_checking = "OFF",
ram_block1a_5.init_file = "instruction_mem.mif",
ram_block1a_5.init_file_layout = "port_a",
ram_block1a_5.logical_ram_name = "ALTSYNCRAM",
ram_block1a_5.mem_init0 = 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF06861,
ram_block1a_5.operation_mode = "single_port",
ram_block1a_5.port_a_address_width = 8,
ram_block1a_5.port_a_data_out_clear = "none",
ram_block1a_5.port_a_data_out_clock = "clock0",
ram_block1a_5.port_a_data_width = 1,
ram_block1a_5.port_a_disable_ce_on_input_registers = "off",
ram_block1a_5.port_a_disable_ce_on_output_registers = "off",
ram_block1a_5.port_a_first_address = 0,
ram_block1a_5.port_a_first_bit_number = 5,
ram_block1a_5.port_a_last_address = 255,
ram_block1a_5.port_a_logical_ram_depth = 256,
ram_block1a_5.port_a_logical_ram_width = 8,
ram_block1a_5.power_up_uninitialized = "false",
ram_block1a_5.ram_block_type = "AUTO",
ram_block1a_5.lpm_type = "cycloneii_ram_block",
ram_block1a_5.lpm_hint = "DONT_POWER_OPTIMIZE=ON";
cycloneii_ram_block ram_block1a_6
(
.clk0(clock0),
.ena0(clocken0),
.portaaddr({address_a_wire[7:0]}),
.portadatain({data_a[6]}),
.portadataout(wire_ram_block1a_6portadataout[0:0]),
.portawe(wren_a),
.portbdataout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_6.connectivity_checking = "OFF",
ram_block1a_6.init_file = "instruction_mem.mif",
ram_block1a_6.init_file_layout = "port_a",
ram_block1a_6.logical_ram_name = "ALTSYNCRAM",
ram_block1a_6.mem_init0 = 256'h8000000000000000000000000000000000000000000000000000000000049186,
ram_block1a_6.operation_mode = "single_port",
ram_block1a_6.port_a_address_width = 8,
ram_block1a_6.port_a_data_out_clear = "none",
ram_block1a_6.port_a_data_out_clock = "clock0",
ram_block1a_6.port_a_data_width = 1,
ram_block1a_6.port_a_disable_ce_on_input_registers = "off",
ram_block1a_6.port_a_disable_ce_on_output_registers = "off",
ram_block1a_6.port_a_first_address = 0,
ram_block1a_6.port_a_first_bit_number = 6,
ram_block1a_6.port_a_last_address = 255,
ram_block1a_6.port_a_logical_ram_depth = 256,
ram_block1a_6.port_a_logical_ram_width = 8,
ram_block1a_6.power_up_uninitialized = "false",
ram_block1a_6.ram_block_type = "AUTO",
ram_block1a_6.lpm_type = "cycloneii_ram_block",
ram_block1a_6.lpm_hint = "DONT_POWER_OPTIMIZE=ON";
cycloneii_ram_block ram_block1a_7
(
.clk0(clock0),
.ena0(clocken0),
.portaaddr({address_a_wire[7:0]}),
.portadatain({data_a[7]}),
.portadataout(wire_ram_block1a_7portadataout[0:0]),
.portawe(wren_a),
.portbdataout()
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_off
`endif
,
.clk1(1'b0),
.clr0(1'b0),
.clr1(1'b0),
.ena1(1'b1),
.portaaddrstall(1'b0),
.portabyteenamasks({1{1'b1}}),
.portbaddr({1{1'b0}}),
.portbaddrstall(1'b0),
.portbbyteenamasks({1{1'b1}}),
.portbdatain({1{1'b0}}),
.portbrewe(1'b0)
`ifdef FORMAL_VERIFICATION
`else
// synopsys translate_on
`endif
// synopsys translate_off
,
.devclrn(1'b1),
.devpor(1'b1)
// synopsys translate_on
);
defparam
ram_block1a_7.connectivity_checking = "OFF",
ram_block1a_7.init_file = "instruction_mem.mif",
ram_block1a_7.init_file_layout = "port_a",
ram_block1a_7.logical_ram_name = "ALTSYNCRAM",
ram_block1a_7.mem_init0 = 256'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF07861,
ram_block1a_7.operation_mode = "single_port",
ram_block1a_7.port_a_address_width = 8,
ram_block1a_7.port_a_data_out_clear = "none",
ram_block1a_7.port_a_data_out_clock = "clock0",
ram_block1a_7.port_a_data_width = 1,
ram_block1a_7.port_a_disable_ce_on_input_registers = "off",
ram_block1a_7.port_a_disable_ce_on_output_registers = "off",
ram_block1a_7.port_a_first_address = 0,
ram_block1a_7.port_a_first_bit_number = 7,
ram_block1a_7.port_a_last_address = 255,
ram_block1a_7.port_a_logical_ram_depth = 256,
ram_block1a_7.port_a_logical_ram_width = 8,
ram_block1a_7.power_up_uninitialized = "false",
ram_block1a_7.ram_block_type = "AUTO",
ram_block1a_7.lpm_type = "cycloneii_ram_block",
ram_block1a_7.lpm_hint = "DONT_POWER_OPTIMIZE=ON";
assign
address_a_wire = address_a,
q_a = {wire_ram_block1a_7portadataout[0], wire_ram_block1a_6portadataout[0], wire_ram_block1a_5portadataout[0], wire_ram_block1a_4portadataout[0], wire_ram_block1a_3portadataout[0], wire_ram_block1a_2portadataout[0], wire_ram_block1a_1portadataout[0], wire_ram_block1a_0portadataout[0]};
endmodule //ss_altsyncram
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ss (
address,
clken,
clock,
data,
wren,
q)/* synthesis synthesis_clearbox = 1 */;
input [7:0] address;
input clken;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
ss_altsyncram ss_altsyncram_component (
.clocken0 (clken),
.wren_a (wren),
.clock0 (clock),
.address_a (address),
.data_a (data),
.q_a (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"
// Retrieval info: PRIVATE: Clken NUMERIC "1"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "instruction_mem.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "NORMAL"
// Retrieval info: CONSTANT: INIT_FILE STRING "instruction_mem.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT NODEFVAL clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ss.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ss.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ss.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ss.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ss_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ss_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ss_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ss_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ss_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
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