condcontrol.v

来自「使用verilog作为CPU设计语言实现单数据通路五级流水线的CPU。具有32个」· Verilog 代码 · 共 34 行

module condcontrol(mp0sel,ir2_op,ir3_op,ov,signal,zero,x3_out31,y3_out31,
ov2branch,zero2branch,signal2branch,a312branch,b312branch);
output mp0sel;
input [5:0]ir2_op,ir3_op;
input ov,signal,zero,x3_out31,y3_out31,ov2branch,zero2branch,signal2branch,a312branch,b312branch;
parameter JMP=6'b 100000;
parameter JEQ=6'b 100001;
parameter JNE=6'b 100010;
parameter JA=6'b 100011;
parameter JB=6'b 100100;
parameter JG=6'b 100101;
parameter JL=6'b 100110;
parameter SUB=6'b 000001;
parameter SUBU=6'b 000011;
parameter SUBI=6'b 010001;
parameter SUBUI=6'b 010011;
wire ir3iscmp;
wire mp0sel;
assign ir3iscmp=(ir3_op==SUB||ir3_op==SUBU||ir3_op==SUBI||ir3_op==SUBUI);
assign 
mp0sel=((ir2_op==JMP)||(ir3iscmp==0&&((ir2_op==JEQ&&zero2branch==1)||(ir2_op==JNE&&zero2branch==0)||
(ir2_op==JG&&ov2branch==1&&signal2branch==1)||(ir2_op==JG&&ov2branch==0&&signal2branch==0&&zero2branch==0)||
(ir2_op==JL&&ov2branch==1&&signal2branch==0)||(ir2_op==JL&&ov2branch==0&&signal2branch==1)||
(x3_out31==0&&y3_out31==0&&((ir2_op==JA&&signal2branch==0&&zero2branch==0)||(ir2_op==JB&&signal2branch==1)))||
(x3_out31==1&&y3_out31==0&&ir2_op==JA)||(x3_out31==0&&y3_out31==1&&ir2_op==JB)||
(x3_out31==1&&y3_out31==1&&((ir2_op==JA&&signal2branch==1)||(ir2_op==JB&&signal2branch==0&&zero2branch==0)))))||
(ir3iscmp==1&&((ir2_op==JEQ&&zero==1)||(ir2_op==JNE&&zero==0)||
(ir2_op==JG&&ov==1&&signal==1)||(ir2_op==JG&&ov==0&&signal==0&&zero==0)||
(ir2_op==JL&&ov==1&&signal==0)||(ir2_op==JL&&ov==0&&signal==1)||
(a312branch==0&&b312branch==0&&((ir2_op==JA&&signal==0&&zero==0)||(ir2_op==JB&&signal==1)))||
(a312branch==1&&b312branch==0&&ir2_op==JA)||(a312branch==0&&b312branch==1&&ir2_op==JB)||
(a312branch==1&&b312branch==1&&((ir2_op==JA&&signal==1)||(ir2_op==JB&&signal==0&&zero==0))))));

endmodule