func_lib.v

使用verilog作为CPU设计语言实现单数据通路五级流水线的CPU。具有32个通用寄存器、一个程序计数器PC、一个标志寄存器FLAG

/*有如下模块
mux2_1     1 路2选 1
mux4_1     1 路4选 1
d_flp
d_flp_32
Reg 
mux5x2_1    5路2 选 1
mux32x4_1   32路4选1
mux32x2_1   32路2选1
decoder5_32 //pc 模块译码用
SignalReg
*/
//0->a
module mux2_1(c,a,b,s );
input a,b,s;
wire n1,n2,n3;
output c;
not(n1,s);//n1->1
and(n2,a,n1);//n2->a
and(n3,b,s);//n3->0
or (c,n2,n3);//c->a
endmodule
//00->a  01->b 
module mux4_1(y,a,b,c,d,s1,s0);
input a,b,c,d,s1,s0;
output y;
wire n1,n2;
mux2_1(n1,a,c,s1);
mux2_1(n2,b,d,s1);
mux2_1(y,n1,n2,s0);
endmodule

module d_flp( q,d,clock, enable,reset ); //模块名及参数定义，范围至endmodule。
input enable,reset, d, clock; //输入端口定义
output q; //输出端口定义
reg q; //寄存器定义
always @( posedge clock or negedge reset ) 
	begin
if(!reset)begin q<=0;			//低电平复位
end
else if(!enable)begin q<=q;     //enable 索存
end
else begin
q<=d;
end
	end
endmodule

module d_flp_32( q,d,clock, enable,reset ); //模块名及参数定义，范围至endmodule。
input enable,reset, clock; //输入端口定义
input [31:0]d;
output[31:0]q; //输出端口定义
reg[31:0] q; //寄存器定义

always @( posedge clock or negedge reset ) 
	begin
if(!reset)begin q<=32'b0;			//低电平复位
end
else if(!enable)begin q<=q;     //enable 索存
end
else begin
q<=d;
end
	end
endmodule


module Reg(out,in,clock,Reg_en,reset);
output [31:0]out;
input  [31:0]in;
input  Reg_en,clock,reset;
d_flp_32 d(out[31:0],in[31:0],clock,Reg_en,reset);
endmodule

module SignalReg (ov2branch,zero2branch,signal2branch,x_highbit,y_highbit,
 ov,zero,signal,x3_out31,y3_out31,						//,bran_a31,bran_b31,,x3_out[31],y3_out[31],
 clock,branch_en,reset);

output ov2branch,zero2branch,signal2branch,x_highbit,y_highbit;
input  ov,zero,signal,signal,x3_out31,y3_out31;
input  clock,branch_en,reset;

d_flp  dflp4(ov2branch,ov,clock,branch_en,reset);
d_flp  dflp3(zero2branch,zero,clock,branch_en,reset);
d_flp  dflp2(signal2branch,signal,clock,branch_en,reset);
d_flp  dflp1(x_highbit,x3_out31,clock,branch_en,reset);
d_flp  dflp0(y_highbit,y3_out31,clock,branch_en,reset);

endmodule
module mux5x2_1(out,in1,in2,s);
output [4:0]out;
input  [4:0]in1,in2;
input  s;

mux2_1 m[4:0](out[4:0],in1[4:0],in2[4:0],s);
endmodule

module mux32x4_1(out,in1,in2,in3,in4,s1,s0);
output [31:0]out;
input  [31:0]in1,in2,in3,in4;
input  s1,s0;

mux4_1 m[31:0](out[31:0],in1[31:0],in2[31:0],in3[31:0],in4[31:0],s1,s0);
endmodule

module mux32x2_1(out,in1,in2,s);
output [31:0]out;
input  [31:0]in1,in2;
input  s;

mux2_1 m[31:0](out[31:0],in1[31:0],in2[31:0],s);
endmodule


module decoder5_32(out,in);
output [31:0]out;
input  [4:0] in;
wire   [4:0] n_in;

not n[4:0](n_in[4:0],in[4:0]);

and(out[0],n_in[4],n_in[3],n_in[2],n_in[1],n_in[0]);
and(out[1],n_in[4],n_in[3],n_in[2],n_in[1],in[0]);
and(out[2],n_in[4],n_in[3],n_in[2],in[1],n_in[0]);
and(out[3],n_in[4],n_in[3],n_in[2],in[1],in[0]);
and(out[4],n_in[4],n_in[3],in[2],n_in[1],n_in[0]);
and(out[5],n_in[4],n_in[3],in[2],n_in[1],in[0]);
and(out[6],n_in[4],n_in[3],in[2],in[1],n_in[0]);
and(out[7],n_in[4],n_in[3],in[2],in[1],in[0]);
and(out[8],n_in[4],in[3],n_in[2],n_in[1],n_in[0]);
and(out[9],n_in[4],in[3],n_in[2],n_in[1],in[0]);
and(out[10],n_in[4],in[3],n_in[2],in[1],n_in[0]);
and(out[11],n_in[4],in[3],n_in[2],in[1],in[0]);
and(out[12],n_in[4],in[3],in[2],n_in[1],n_in[0]);

and(out[13],n_in[4],in[3],in[2],n_in[1],in[0]);
and(out[14],n_in[4],in[3],in[2],in[1],n_in[0]);
and(out[15],n_in[4],in[3],in[2],in[1],in[0]);
and(out[16],in[4],n_in[3],n_in[2],n_in[1],n_in[0]);
and(out[17],in[4],n_in[3],n_in[2],n_in[1],in[0]);
and(out[18],in[4],n_in[3],n_in[2],in[1],n_in[0]);
and(out[19],in[4],n_in[3],n_in[2],in[1],in[0]);
and(out[20],in[4],n_in[3],in[2],n_in[1],n_in[0]);
and(out[21],in[4],n_in[3],in[2],n_in[1],in[0]);
and(out[22],in[4],n_in[3],in[2],in[1],n_in[0]);
and(out[23],in[4],n_in[3],in[2],in[1],in[0]);
and(out[24],in[4],in[3],n_in[2],n_in[1],n_in[0]);
and(out[25],in[4],in[3],n_in[2],n_in[1],in[0]);
and(out[26],in[4],in[3],n_in[2],in[1],n_in[0]);
and(out[27],in[4],in[3],n_in[2],in[1],in[0]);
and(out[28],in[4],in[3],in[2],n_in[1],n_in[0]);

and(out[29],in[4],in[3],in[2],n_in[1],in[0]);
and(out[30],in[4],in[3],in[2],in[1],n_in[0]);
and(out[31],in[4],in[3],in[2],in[1],in[0]);

endmodule

module AddSub(AddSubY,CY,OV,AddSubA,AddSubB,AddSubOP);
output [31:0] AddSubY;
output CY,OV;
input [31:0] AddSubA,AddSubB;
input AddSubOP;
wire [31:0] AddB;
xor_32 xor_32_1(AddB,AddSubB,AddSubOP);
Adder_32 Adder_32_1(AddSubY,CY,OV,AddSubA,AddB,AddSubOP);
endmodule

module xor_32(xorout,xorin,Sub);
output [31:0] xorout;
input [31:0] xorin;
input Sub;
wire [31:0] temp;
assign temp = {32{Sub}};
assign xorout = xorin^temp;
endmodule

module Adder_32(AddY,CY,OV,AddA,AddB,Cin);
output [31:0] AddY;
output CY,OV;
input [31:0] AddA,AddB;
input Cin;
wire [3:0] C,G,P;
assign C[0] =Cin;
Adder_8 Adder_80(AddY[7:0],G[0],P[0],AddA[7:0],AddB[7:0],C[0]);
assign C[1] = G[0]|P[0]&C[0];
Adder_8 Adder_81(AddY[15:8],G[1],P[1],AddA[15:8],AddB[15:8],C[1]);
assign C[2] = G[1]|P[1]&G[0]|P[1]&P[0]&C[0];
Adder_8 Adder_82(AddY[23:16],G[2],P[2],AddA[23:16],AddB[23:16],C[2]);
assign C[3] = G[2]|P[2]&G[1]|P[2]&P[1]&G[0]|P[2]&P[1]&P[0]&C[0];
Adder_8 Adder_83(AddY[31:24],G[3],P[3],AddA[31:24],AddB[31:24],C[3]);
assign CY = G[3]|P[3]&G[2]|P[3]&P[2]&G[1]|P[3]&P[2]&P[1]&G[0]|P[3]&P[2]&P[1]&P[0]&C[0];
assign OV = CY^C[3];
endmodule

module Adder_8(AddY,Gout,Pout,AddA,AddB,Cin);
output [7:0] AddY;
output Gout,Pout;
input [7:0] AddA,AddB;
input Cin;
wire [7:0] P,G,C;
assign G = AddA&AddB;
assign P = AddA^AddB;
assign Gout = G[7]|P[7]&G[6]|P[7]&P[6]&G[5]|P[7]&P[6]&P[5]&G[4]|P[7]&P[6]&P[5]&P[4]&G[3]|P[7]&P[6]&P[5]&P[4]&P[3]&G[2]|P[7]&P[6]&P[5]&P[4]&P[3]&P[2]&G[1]|P[7]&P[6]&P[5]&P[4]&P[3]&P[2]&P[1]&G[0];
assign	Pout = P[7]&P[6]&P[5]&P[4]&P[3]&P[2]&P[1]&P[0];
assign  C[0] = Cin;
assign 	C[1] = G[0]|P[0]&C[0];
assign  C[2] = G[1]|P[1]&G[0]|P[1]&P[0]&C[0];
assign  C[3] = G[2]|P[2]&G[1]|P[2]&P[1]&G[0]|P[2]&P[1]&P[0]&C[0];
assign  C[4] = G[3]|P[3]&G[2]|P[3]&P[2]&G[1]|P[3]&P[2]&P[1]&G[0]|P[3]&P[2]&P[1]&P[0]&C[0];
assign  C[5] = G[4]|P[4]&G[3]|P[4]&P[3]&G[2]|P[4]&P[3]&P[2]&G[1]|P[4]&P[3]&P[2]&P[1]&G[0]|P[4]&P[3]&P[2]&P[1]&P[0]&C[0];
assign	C[6] = G[5]|P[5]&G[4]|P[5]&P[4]&G[3]|P[5]&P[4]&P[3]&G[2]|P[5]&P[4]&P[3]&P[2]&G[1]|P[5]&P[4]&P[3]&P[2]&P[1]&G[0]|P[5]&P[4]&P[3]&P[2]&P[1]&P[0]&C[0];
assign  C[7] = G[6]|P[6]&G[5]|P[6]&P[5]&G[4]|P[6]&P[5]&P[4]&G[3]|P[6]&P[5]&P[4]&P[3]&G[2]|P[6]&P[5]&P[4]&P[3]&P[2]&G[1]|P[6]&P[5]&P[4]&P[3]&P[2]&P[1]&G[0]|P[6]&P[5]&P[4]&P[3]&P[2]&P[1]&P[0]&C[0];
assign	AddY = P^C;
endmodule