coder_8_3.hier_info

用verilog HDL实现了83编码器.

|Coder_8_3
EN => A2~3.OUTPUTSELECT
EN => A1~5.OUTPUTSELECT
EN => A0~6.OUTPUTSELECT
EN => GS~7.OUTPUTSELECT
EN => EO~8.OUTPUTSELECT
I0 => reduce_nor~6.IN0
I0 => always0~7.IN0
I1 => reduce_nor~5.IN0
I1 => always0~6.IN0
I2 => reduce_nor~4.IN0
I2 => always0~5.IN0
I3 => reduce_nor~3.IN0
I3 => always0~3.IN0
I4 => reduce_nor~2.IN0
I4 => always0~4.IN0
I5 => reduce_nor~1.IN0
I5 => always0~0.IN0
I6 => reduce_nor~0.IN0
I6 => always0~1.IN0
I7 => always0~2.IN0
A2 <= A2~3.DB_MAX_OUTPUT_PORT_TYPE
A1 <= A1~5.DB_MAX_OUTPUT_PORT_TYPE
A0 <= A0~6.DB_MAX_OUTPUT_PORT_TYPE
GS <= GS~7.DB_MAX_OUTPUT_PORT_TYPE
EO <= EO~8.DB_MAX_OUTPUT_PORT_TYPE