coder_8_3.fit.summary

来自「用verilog HDL实现了83编码器.」· SUMMARY 代码 · 共 11 行

Flow Status : Successful - Tue Aug 08 10:48:04 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : Coder_8_3
Top-level Entity Name : Coder_8_3
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 5 / 32 ( 15 % )
Total pins : 18 / 36 ( 50 % )
Device : EPM7032SLC44-5
Timing Models : Final