coder_8_3.map.eqn

用verilog HDL实现了83编码器.

--A1L9 is EO~28
A1L9_p1_out = !EN & I6 & I5 & I7 & I1 & I2 & I4 & I3 & I0;
A1L9_or_out = A1L9_p1_out;
A1L9 = !(A1L9_or_out);


--A1L6 is A2~31
A1L6_p1_out = I4 & I6 & I7 & I5;
A1L6_or_out = A1L6_p1_out # EN;
A1L6 = A1L6_or_out;


--A1L2 is A0~96
A1L2_p1_out = !I4 & I5 & I7;
A1L2_p2_out = I5 & I7 & I1 & I3;
A1L2_p3_out = I5 & I7 & I3 & !I2;
A1L2_p4_out = I7 & !I6;
A1L2_or_out = EN # A1L2_p1_out # A1L2_p2_out # A1L2_p3_out # A1L2_p4_out;
A1L2 = A1L2_or_out;


--A1L11 is GS~24
A1L11_p1_out = I5 & I6 & I7 & I1 & I2 & I4 & I3 & I0;
A1L11_or_out = A1L11_p1_out # EN;
A1L11 = A1L11_or_out;


--A1L4 is A1~98
A1L4_p1_out = !I5 & I7 & I6;
A1L4_p2_out = I7 & I6 & I2 & I3;
A1L4_p3_out = I7 & I6 & !I4;
A1L4_or_out = A1L4_p1_out # A1L4_p2_out # A1L4_p3_out # EN;
A1L4 = A1L4_or_out;


--EN is EN
--operation mode is input

EN = INPUT();


--I0 is I0
--operation mode is input

I0 = INPUT();


--I1 is I1
--operation mode is input

I1 = INPUT();


--I2 is I2
--operation mode is input

I2 = INPUT();


--I3 is I3
--operation mode is input

I3 = INPUT();


--I4 is I4
--operation mode is input

I4 = INPUT();


--I5 is I5
--operation mode is input

I5 = INPUT();


--I6 is I6
--operation mode is input

I6 = INPUT();


--I7 is I7
--operation mode is input

I7 = INPUT();


--EO is EO
--operation mode is output

EO = OUTPUT(A1L9);


--A2 is A2
--operation mode is output

A2 = OUTPUT(A1L6);


--A0 is A0
--operation mode is output

A0 = OUTPUT(A1L2);


--GS is GS
--operation mode is output

GS = OUTPUT(A1L11);


--A1 is A1
--operation mode is output

A1 = OUTPUT(A1L4);