8_jjfq.vhd

用VHADL和Verilog HDL实现带进位的8位加减法器。

-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 7.2 Build 151 09/26/2007 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY \8_jjfq\ IS 
	port
	(
		a0 :  IN  STD_LOGIC;
		b0 :  IN  STD_LOGIC;
		sub :  IN  STD_LOGIC;
		a1 :  IN  STD_LOGIC;
		b1 :  IN  STD_LOGIC;
		a2 :  IN  STD_LOGIC;
		b2 :  IN  STD_LOGIC;
		a3 :  IN  STD_LOGIC;
		b3 :  IN  STD_LOGIC;
		a4 :  IN  STD_LOGIC;
		b4 :  IN  STD_LOGIC;
		a5 :  IN  STD_LOGIC;
		b5 :  IN  STD_LOGIC;
		a6 :  IN  STD_LOGIC;
		b6 :  IN  STD_LOGIC;
		a7 :  IN  STD_LOGIC;
		b7 :  IN  STD_LOGIC;
		s0 :  OUT  STD_LOGIC;
		s1 :  OUT  STD_LOGIC;
		s2 :  OUT  STD_LOGIC;
		s3 :  OUT  STD_LOGIC;
		s4 :  OUT  STD_LOGIC;
		s5 :  OUT  STD_LOGIC;
		s6 :  OUT  STD_LOGIC;
		s7 :  OUT  STD_LOGIC;
		carry_out :  OUT  STD_LOGIC
	);
END \8_jjfq\;

ARCHITECTURE bdf_type OF \8_jjfq\ IS 

component jjdy
	PORT(a : IN STD_LOGIC;
		 carry_in : IN STD_LOGIC;
		 b : IN STD_LOGIC;
		 sub : IN STD_LOGIC;
		 s : OUT STD_LOGIC;
		 carry_out : OUT STD_LOGIC
	);
end component;

signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_2 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_3 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_4 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_5 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_6 :  STD_LOGIC;


BEGIN 



b2v_inst : jjdy
PORT MAP(a => a0,
		 carry_in => sub,
		 b => b0,
		 sub => sub,
		 s => s0,
		 carry_out => SYNTHESIZED_WIRE_0);

b2v_inst1 : jjdy
PORT MAP(a => a1,
		 carry_in => SYNTHESIZED_WIRE_0,
		 b => b1,
		 sub => sub,
		 s => s1,
		 carry_out => SYNTHESIZED_WIRE_1);

b2v_inst2 : jjdy
PORT MAP(a => a2,
		 carry_in => SYNTHESIZED_WIRE_1,
		 b => b2,
		 sub => sub,
		 s => s2,
		 carry_out => SYNTHESIZED_WIRE_2);

b2v_inst3 : jjdy
PORT MAP(a => a3,
		 carry_in => SYNTHESIZED_WIRE_2,
		 b => b3,
		 sub => sub,
		 s => s3,
		 carry_out => SYNTHESIZED_WIRE_3);

b2v_inst4 : jjdy
PORT MAP(a => a4,
		 carry_in => SYNTHESIZED_WIRE_3,
		 b => b4,
		 sub => sub,
		 s => s4,
		 carry_out => SYNTHESIZED_WIRE_4);

b2v_inst5 : jjdy
PORT MAP(a => a5,
		 carry_in => SYNTHESIZED_WIRE_4,
		 b => b5,
		 sub => sub,
		 s => s5,
		 carry_out => SYNTHESIZED_WIRE_5);

b2v_inst6 : jjdy
PORT MAP(a => a6,
		 carry_in => SYNTHESIZED_WIRE_5,
		 b => b6,
		 sub => sub,
		 s => s6,
		 carry_out => SYNTHESIZED_WIRE_6);

b2v_inst7 : jjdy
PORT MAP(a => a7,
		 carry_in => SYNTHESIZED_WIRE_6,
		 b => b7,
		 sub => sub,
		 s => s7,
		 carry_out => carry_out);

END;