8_jjfq.v

用VHADL和Verilog HDL实现带进位的8位加减法器。

// Copyright (C) 1991-2007 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

module \8_jjfq (
	a0,
	b0,
	sub,
	a1,
	b1,
	a2,
	b2,
	a3,
	b3,
	a4,
	b4,
	a5,
	b5,
	a6,
	b6,
	a7,
	b7,
	s0,
	s1,
	s2,
	s3,
	s4,
	s5,
	s6,
	s7,
	carry_out
);

input	a0;
input	b0;
input	sub;
input	a1;
input	b1;
input	a2;
input	b2;
input	a3;
input	b3;
input	a4;
input	b4;
input	a5;
input	b5;
input	a6;
input	b6;
input	a7;
input	b7;
output	s0;
output	s1;
output	s2;
output	s3;
output	s4;
output	s5;
output	s6;
output	s7;
output	carry_out;

wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;
wire	SYNTHESIZED_WIRE_3;
wire	SYNTHESIZED_WIRE_4;
wire	SYNTHESIZED_WIRE_5;
wire	SYNTHESIZED_WIRE_6;





jjdy	b2v_inst(.a(a0),
.carry_in(sub),.b(b0),.sub(sub),.s(s0),.carry_out(SYNTHESIZED_WIRE_0));

jjdy	b2v_inst1(.a(a1),
.carry_in(SYNTHESIZED_WIRE_0),.b(b1),.sub(sub),.s(s1),.carry_out(SYNTHESIZED_WIRE_1));

jjdy	b2v_inst2(.a(a2),
.carry_in(SYNTHESIZED_WIRE_1),.b(b2),.sub(sub),.s(s2),.carry_out(SYNTHESIZED_WIRE_2));

jjdy	b2v_inst3(.a(a3),
.carry_in(SYNTHESIZED_WIRE_2),.b(b3),.sub(sub),.s(s3),.carry_out(SYNTHESIZED_WIRE_3));

jjdy	b2v_inst4(.a(a4),
.carry_in(SYNTHESIZED_WIRE_3),.b(b4),.sub(sub),.s(s4),.carry_out(SYNTHESIZED_WIRE_4));

jjdy	b2v_inst5(.a(a5),
.carry_in(SYNTHESIZED_WIRE_4),.b(b5),.sub(sub),.s(s5),.carry_out(SYNTHESIZED_WIRE_5));

jjdy	b2v_inst6(.a(a6),
.carry_in(SYNTHESIZED_WIRE_5),.b(b6),.sub(sub),.s(s6),.carry_out(SYNTHESIZED_WIRE_6));

jjdy	b2v_inst7(.a(a7),
.carry_in(SYNTHESIZED_WIRE_6),.b(b7),.sub(sub),.s(s7),.carry_out(carry_out));


endmodule