reg_counter.srs

程序补充说明：时钟输入：在每个时钟的正沿或负沿对数据进行处理。时钟的正沿有效还是负沿有效

#
#
#
# Created by Synplify Verilog HDL Compiler version 3.1.0, Build 049R from Synplicity, Inc.
# Copyright 1994-2004 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on Tue Jan 10 01:15:31 2006
#
#
#OPTIONS:"|-primux|-fixsmult|-sdff_counter|-infer_seqShift|-nram|-divnmod|-I|C:\\prj\\Example-4-1\\|-I|C:\\eda\\synplicity\\fpga_81\\lib|-v2001|-devicelib|C:\\eda\\synplicity\\fpga_81\\lib\\xilinx\\unisim.v|-sm|-fid2|-sharing|off|-encrypt|-ui|-pro|-ram|-ll|2000"
#CUR:"C:\\eda\\synplicity\\fpga_81\\bin\\c_ver.exe":1115125636
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\xilinx\\unisim.v":1113287638
#CUR:"C:\\eda\\synplicity\\fpga_81\\lib\\xilinx\\unisim.v":1113287638
#CUR:"C:\\prj\\Example-4-1\\reg_counter.v":1136826928
#CUR:"C:\\prj\\Example-4-1\\reg_counter.v":1136826928
f "C:\eda\synplicity\fpga_81\lib\xilinx\unisim.v"; # file 0
af .is_verilog 1;
f "C:\prj\Example-4-1\reg_counter.v"; # file 1
af .is_verilog 1;
@E
@ 
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