tb_count_4.v

来自「VHDL源码其中“music_rom”使用FPGA厂商提供的工具生成的」· Verilog 代码 · 共 52 行

module tb_count_4();
reg clk,rst,entable,load;
reg[3:0] d_in;
wire[3:0] count;
reg[1:0] up_down;
always
    begin
        clk=0;
        #10;
        clk=1;
        #10;
    end
        
initial
begin
    rst=1;
    #15;
    rst=0;
end

initial
begin
entable=1;
load=0;
#18;
load=1;
#10;
load=0;
#22;
entable=0;
end

initial
begin
    d_in=4'b0;
    #12;
    d_in=4'b0110;  
end

initial 
begin 
up_down=2'b00;
#35;
up_down=2'b01;
#58;
up_down=2'b10;
end

Count_4 count4(count,up_down,clk,rst,d_in,load,entable);
    
endmodule