count_4.v

来自「VHDL源码其中“music_rom”使用FPGA厂商提供的工具生成的」· Verilog 代码 · 共 20 行

module Count_4(count,up_down,clock,reset,D_in,load,entable);
    input[1:0] up_down;
    input D_in;
    wire[3:0] D_in;
    input clock,reset,load,entable;
    output count;
    reg[3:0] count;
    
    always @(negedge clock)
    if(reset==1) count<=4'b0;else
    if(load==1) count<=D_in;else
    if(entable==0) 
    case (up_down)
    2'b01: count<=count+1;
    2'b10: count<=count-1;
    default count<=count;
endcase
endmodule