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<TD ALIGN="LEFT">OUTDATA_ACLR_A</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WRCONTROL_ACLR_A</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">INDATA_ACLR_A</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">BYTEENA_ACLR_A</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WIDTH_B</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WIDTHAD_B</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">NUMWORDS_B</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">INDATA_REG_B</TD>
<TD ALIGN="LEFT">CLOCK1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WRCONTROL_WRADDRESS_REG_B</TD>
<TD ALIGN="LEFT">CLOCK1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">RDCONTROL_REG_B</TD>
<TD ALIGN="LEFT">CLOCK1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">ADDRESS_REG_B</TD>
<TD ALIGN="LEFT">CLOCK1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">OUTDATA_REG_B</TD>
<TD ALIGN="LEFT">UNREGISTERED</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">BYTEENA_REG_B</TD>
<TD ALIGN="LEFT">CLOCK1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">INDATA_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WRCONTROL_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">ADDRESS_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">OUTDATA_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">RDCONTROL_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">BYTEENA_ACLR_B</TD>
<TD ALIGN="LEFT">NONE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WIDTH_BYTEENA_A</TD>
<TD ALIGN="LEFT">4</TD>
<TD ALIGN="LEFT">Integer</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">WIDTH_BYTEENA_B</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">RAM_BLOCK_TYPE</TD>
<TD ALIGN="LEFT">M4K</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">BYTE_SIZE</TD>
<TD ALIGN="LEFT">8</TD>
<TD ALIGN="LEFT">Integer</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">READ_DURING_WRITE_MODE_MIXED_PORTS</TD>
<TD ALIGN="LEFT">DONT_CARE</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">INIT_FILE</TD>
<TD ALIGN="LEFT">onchip_ram.hex</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">INIT_FILE_LAYOUT</TD>
<TD ALIGN="LEFT">PORT_A</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">MAXIMUM_DEPTH</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">CLOCK_ENABLE_INPUT_A</TD>
<TD ALIGN="LEFT">NORMAL</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">CLOCK_ENABLE_INPUT_B</TD>
<TD ALIGN="LEFT">NORMAL</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">CLOCK_ENABLE_OUTPUT_A</TD>
<TD ALIGN="LEFT">NORMAL</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">CLOCK_ENABLE_OUTPUT_B</TD>
<TD ALIGN="LEFT">NORMAL</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">DEVICE_FAMILY</TD>
<TD ALIGN="LEFT">Cyclone II</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">CBXI_PARAMETER</TD>
<TD ALIGN="LEFT">altsyncram_fh01</TD>
<TD ALIGN="LEFT">Untyped</TD>
</TR>
</TABLE>
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".<br>
<P><A NAME="15"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Equations</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<a href="file:///c:/Pabst/test_scratch/test/small/small.map.eqn.htm">Analysis & Synthesis Equations</a><BR>
<P><A NAME="16"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Messages</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<PRE>
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 146 04/13/2005 SJ Full Version
    Info: Processing started: Wed Apr 20 20:10:58 2005
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off small -c small
Info: Found 2 design units, including 0 entities, in source file altera_vhdl_support.vhd
    Info: Found design unit 1: altera_vhdl_support_lib
    Info: Found design unit 2: altera_vhdl_support_lib-body
Info: Using design file small.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: small
Info: Elaborating entity "small" for the top level hierarchy
Info: Using design file small_2C35.vhd, which is not specified as a design file for the current project, but contains definitions for 12 design units and 6 entities in project
    Info: Found design unit 1: cpu_data_master_arbitrator-europa
    Info: Found design unit 2: cpu_instruction_master_arbitrator-europa
    Info: Found design unit 3: led_pio_s1_arbitrator-europa
    Info: Found design unit 4: onchip_ram_s1_arbitrator-europa
    Info: Found design unit 5: small_2C35_reset_clk_domain_synch_module-europa
    Info: Found design unit 6: small_2C35-europa
    Info: Found entity 1: cpu_data_master_arbitrator
    Info: Found entity 2: cpu_instruction_master_arbitrator
    Info: Found entity 3: led_pio_s1_arbitrator
    Info: Found entity 4: onchip_ram_s1_arbitrator
    Info: Found entity 5: small_2C35_reset_clk_domain_synch_module
    Info: Found entity 6: small_2C35
Info: Elaborating entity "small_2C35" for hierarchy "small_2C35:inst"
Info: Elaborating entity "cpu_data_master_arbitrator" for hierarchy "small_2C35:inst|cpu_data_master_arbitrator:the_cpu_data_master"
Info: Elaborating entity "cpu_instruction_master_arbitrator" for hierarchy "small_2C35:inst|cpu_instruction_master_arbitrator:the_cpu_instruction_master"
Info: (10035) Verilog HDL or VHDL information at small_2C35.vhd(136): object "active_and_waiting_last_time" declared but not used
Info: (10035) Verilog HDL or VHDL information at small_2C35.vhd(137): object "cpu_instruction_master_address_last_time" declared but not used
Info: (10035) Verilog HDL or VHDL information at small_2C35.vhd(138): object "cpu_instruction_master_read_last_time" declared but not used
Info: Using design file cpu.vhd, which is not specified as a design file for the current project, but contains definitions for 4 design units and 2 entities in project
    Info: Found design unit 1: cpu_rf_module-europa
    Info: Found design unit 2: cpu-europa
    Info: Found entity 1: cpu_rf_module
    Info: Found entity 2: cpu
Info: Elaborating entity "cpu" for hierarchy "small_2C35:inst|cpu:the_cpu"
Info: Using design file cpu_test_bench.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: cpu_test_bench-europa
    Info: Found entity 1: cpu_test_bench
Info: Elaborating entity "cpu_test_bench" for hierarchy "small_2C35:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench"
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(58): object "D_inst" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(187): object "W_vinst" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(188): object "av_ld_data_aligned_unfiltered_0_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(189): object "av_ld_data_aligned_unfiltered_10_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(190): object "av_ld_data_aligned_unfiltered_11_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(191): object "av_ld_data_aligned_unfiltered_12_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(192): object "av_ld_data_aligned_unfiltered_13_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(193): object "av_ld_data_aligned_unfiltered_14_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(194): object "av_ld_data_aligned_unfiltered_15_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(195): object "av_ld_data_aligned_unfiltered_16_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(196): object "av_ld_data_aligned_unfiltered_17_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(197): object "av_ld_data_aligned_unfiltered_18_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(198): object "av_ld_data_aligned_unfiltered_19_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(199): object "av_ld_data_aligned_unfiltered_1_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(200): object "av_ld_data_aligned_unfiltered_20_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(201): object "av_ld_data_aligned_unfiltered_21_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(202): object "av_ld_data_aligned_unfiltered_22_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(203): object "av_ld_data_aligned_unfiltered_23_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(204): object "av_ld_data_aligned_unfiltered_24_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(205): object "av_ld_data_aligned_unfiltered_25_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(206): object "av_ld_data_aligned_unfiltered_26_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(207): object "av_ld_data_aligned_unfiltered_27_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(208): object "av_ld_data_aligned_unfiltered_28_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(209): object "av_ld_data_aligned_unfiltered_29_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(210): object "av_ld_data_aligned_unfiltered_2_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(211): object "av_ld_data_aligned_unfiltered_30_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(212): object "av_ld_data_aligned_unfiltered_31_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(213): object "av_ld_data_aligned_unfiltered_3_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(214): object "av_ld_data_aligned_unfiltered_4_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(215): object "av_ld_data_aligned_unfiltered_5_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(216): object "av_ld_data_aligned_unfiltered_6_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(217): object "av_ld_data_aligned_unfiltered_7_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(218): object "av_ld_data_aligned_unfiltered_8_is_x" declared but not used
Info: (10035) Verilog HDL or VHDL information at cpu_test_bench.vhd(219): object "av_ld_data_aligned_unfiltered_9_is_x" declared but not used
Warning: (10037) Verilog HDL or VHDL warning at cpu_test_bench.vhd(234): condition expression evaluates to a constant
Info: Elaborating entity "cpu_rf_module" for hierarchy "small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf"
Info: Found 1 design units, including 1 entities, in source file ../../../../quartus/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_vuo1.tdf
    Info: Found entity 1: altsyncram_vuo1
Info: Elaborating entity "altsyncram_vuo1" for hierarchy "small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_vuo1:auto_generated"
Info: Elaborating entity "led_pio_s1_arbitrator" for hierarchy "small_2C35:inst|led_pio_s1_arbitrator:the_led_pio_s1"
Warning: Output port "cpu_data_master_read_data_valid_led_pio_s1" at small_2C35.vhd(261) has no driver
Info: Using design file led_pio.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: led_pio-europa
    Info: Found entity 1: led_pio
Info: Elaborating entity "led_pio" for hierarchy "small_2C35:inst|led_pio:the_led_pio"
Info: Elaborating entity "onchip_ram_s1_arbitrator" for hierarchy "small_2C35:inst|onchip_ram_s1_arbitrator:the_onchip_ram_s1"
Info: Using design file onchip_ram.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: onchip_ram-europa
    Info: Found entity 1: onchip_ram
Info: Elaborating entity "onchip_ram" for hierarchy "small_2C35:inst|onchip_ram:the_onchip_ram"
Info: Elaborating entity "altsyncram" for hierarchy "small_2C35:inst|onchip_ram:the_onchip_ram|altsyncram:the_altsyncram"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_fh01.tdf
    Info: Found entity 1: altsyncram_fh01
Info: Elaborating entity "altsyncram_fh01" for hierarchy "small_2C35:inst|onchip_ram:the_onchip_ram|altsyncram:the_altsyncram|altsyncram_fh01:auto_generated"
Warning: Memory depth value (512) in design file differs from memory depth value (1) in Memory Initialization File -- setting initial value for remaining addresses to 0
Info: Elaborating entity "small_2C35_reset_clk_domain_synch_module" for hierarchy "small_2C35:inst|small_2C35_reset_clk_domain_synch_module:small_2C35_reset_clk_domain_synch"
Warning: Reduced register "small_2C35:inst|onchip_ram_s1_arbitrator:the_onchip_ram_s1|d1_reasons_to_wait" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ienable_reg[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[31]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[30]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[29]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[28]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[27]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[26]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[25]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[24]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[22]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[21]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[20]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[19]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[18]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[9]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|cpu:the_cpu|W_ipending_reg[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "small_2C35:inst|onchip_ram_s1_arbitrator:the_onchip_ram_s1|onchip_ram_s1_slavearbiterlockenable" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "small_2C35:inst|onchip_ram_s1_arbitrator:the_onchip_ram_s1|onchip_ram_s1_arb_addend[0]" merged to single register "small_2C35:inst|onchip_ram_s1_arbitrator:the_onchip_ram_s1|onchip_ram_s1_arb_addend[1]", power-up level changed
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 935 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 8 output pins
    Info: Implemented 861 logic cells
    Info: Implemented 64 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 38 warnings
    Info: Processing ended: Wed Apr 20 20:11:47 2005
    Info: Elapsed time: 00:00:50
</PRE>
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