small.map.rpt.htm
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1,668 行
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Allow Any Shift Register Size For Recognition</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maximum Number of M4K Memory Blocks</TD>
<TD ALIGN="LEFT">-1</TD>
<TD ALIGN="LEFT">-1</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Ignore translate_off and translate_on Synthesis Directives</TD>
<TD ALIGN="LEFT">Off</TD>
<TD ALIGN="LEFT">Off</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Show Parameter Settings Tables in Synthesis Report</TD>
<TD ALIGN="LEFT">On</TD>
<TD ALIGN="LEFT">On</TD>
</TR>
</TABLE>
<P><A NAME="4"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Source Files Read</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>File Name with User-Entered Path</TH>
<TH>Used in Netlist</TH>
<TH>File Type</TH>
<TH>File Name with Absolute Path</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altera_vhdl_support.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">User VHDL File </TD>
<TD ALIGN="LEFT">c:/Pabst/test_scratch/test/small/altera_vhdl_support.vhd</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">small.bdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/Pabst/test_scratch/test/small/small.bdf</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">small_2C35.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/Pabst/test_scratch/test/small/small_2C35.vhd</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">cpu.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Encrypted File </TD>
<TD ALIGN="LEFT">c:/Pabst/test_scratch/test/small/cpu.vhd</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">cpu_test_bench.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/Pabst/test_scratch/test/small/cpu_test_bench.vhd</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altsyncram.tdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Megafunction </TD>
<TD ALIGN="LEFT">c:/quartus/libraries/megafunctions/altsyncram.tdf</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">stratix_ram_block.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/quartus/libraries/megafunctions/stratix_ram_block.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">lpm_mux.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/quartus/libraries/megafunctions/lpm_mux.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">lpm_decode.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/quartus/libraries/megafunctions/lpm_decode.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">aglobal50.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/quartus/libraries/megafunctions/aglobal50.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altsyncram.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/quartus/libraries/megafunctions/altsyncram.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">a_rdenreg.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/quartus/libraries/megafunctions/a_rdenreg.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altrom.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/quartus/libraries/megafunctions/altrom.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altram.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/quartus/libraries/megafunctions/altram.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altdpram.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/quartus/libraries/megafunctions/altdpram.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">altqpram.inc</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/quartus/libraries/megafunctions/altqpram.inc</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">db/altsyncram_vuo1.tdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Auto-Generated Megafunction </TD>
<TD ALIGN="LEFT">c:/Pabst/test_scratch/test/small/db/altsyncram_vuo1.tdf</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">led_pio.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/Pabst/test_scratch/test/small/led_pio.vhd</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">onchip_ram.vhd</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Other </TD>
<TD ALIGN="LEFT">c:/Pabst/test_scratch/test/small/onchip_ram.vhd</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">db/altsyncram_fh01.tdf</TD>
<TD ALIGN="LEFT">yes</TD>
<TD ALIGN="LEFT">Auto-Generated Megafunction </TD>
<TD ALIGN="LEFT">c:/Pabst/test_scratch/test/small/db/altsyncram_fh01.tdf</TD>
</TR>
</TABLE>
<P><A NAME="5"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Resource Usage Summary</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Resource</TH>
<TH>Usage</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total combinational functions</TD>
<TD ALIGN="LEFT">555</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Logic element usage by number of LUT inputs</TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- 4 input functions</TD>
<TD ALIGN="LEFT">263</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- 3 input functions</TD>
<TD ALIGN="LEFT">250</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- <=2 input functions</TD>
<TD ALIGN="LEFT">42</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- Combinational cells for routing</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Logic elements by mode</TD>
<TD ALIGN="LEFT"> </TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- normal mode</TD>
<TD ALIGN="LEFT">479</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> -- arithmetic mode</TD>
<TD ALIGN="LEFT">76</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total registers</TD>
<TD ALIGN="LEFT">306</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">I/O pins</TD>
<TD ALIGN="LEFT">10</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total memory bits</TD>
<TD ALIGN="LEFT">17408</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maximum fan-out node</TD>
<TD ALIGN="LEFT">osc_clk[0]</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Maximum fan-out</TD>
<TD ALIGN="LEFT">370</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Total fan-out</TD>
<TD ALIGN="LEFT">4019</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">Average fan-out</TD>
<TD ALIGN="LEFT">4.30</TD>
</TR>
</TABLE>
<P><A NAME="6"><HR></A></P>
<TABLE WIDTH="100%" BORDER="0"><TR VALIGN="TOP">
<TD><H2>Analysis & Synthesis Resource Utilization by Entity</H2></TD>
<TD ALIGN="RIGHT"><A HREF="#top">Top</a></TD></TR></TABLE>
<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Compilation Hierarchy Node</TH>
<TH>LC Combinationals</TH>
<TH>LC Registers</TH>
<TH>Memory Bits</TH>
<TH>DSP Elements</TH>
<TH>DSP 9x9</TH>
<TH>DSP 18x18</TH>
<TH>Pins</TH>
<TH>Virtual Pins</TH>
<TH>Full Hierarchy Name</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">|small</TD>
<TD ALIGN="LEFT">555 (0)</TD>
<TD ALIGN="LEFT">306 (0)</TD>
<TD ALIGN="LEFT">17408</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">10</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">|small</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |small_2C35:inst|</TD>
<TD ALIGN="LEFT">555 (0)</TD>
<TD ALIGN="LEFT">306 (0)</TD>
<TD ALIGN="LEFT">17408</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">|small|small_2C35:inst</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |cpu:the_cpu|</TD>
<TD ALIGN="LEFT">528 (528)</TD>
<TD ALIGN="LEFT">292 (291)</TD>
<TD ALIGN="LEFT">1024</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">|small|small_2C35:inst|cpu:the_cpu</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |cpu_rf_module:cpu_rf|</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">1024</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">|small|small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |altsyncram:the_altsyncram|</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">1024</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">|small|small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |altsyncram_vuo1:auto_generated|</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">1024</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">|small|small_2C35:inst|cpu:the_cpu|cpu_rf_module:cpu_rf|altsyncram:the_altsyncram|altsyncram_vuo1:auto_generated</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |cpu_test_bench:the_cpu_test_bench|</TD>
<TD ALIGN="LEFT">0 (0)</TD>
<TD ALIGN="LEFT">1 (1)</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">|small|small_2C35:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT"> |cpu_data_master_arbitrator:the_cpu_data_master|</TD>
<TD ALIGN="LEFT">2 (2)</TD>
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