vga_colour_bar.map.rpt

用verilog hdl实现的VGA显示彩条信号

+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
; 12:1               ; 3 bits    ; 24 ALUTs      ; 15 ALUTs             ; 9 ALUTs                ; Yes        ; |vga_colour_bar|h_state[0]~reg0 ;
; 12:1               ; 2 bits    ; 16 ALUTs      ; 4 ALUTs              ; 12 ALUTs               ; Yes        ; |vga_colour_bar|v_state[0]~reg0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+


+--------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |vga_colour_bar ;
+----------------+-------+-------------------------------------------------------+
; Parameter Name ; Value ; Type                                                  ;
+----------------+-------+-------------------------------------------------------+
; h_video        ; 000   ; Unsigned Binary                                       ;
; h_front        ; 001   ; Unsigned Binary                                       ;
; h_sync         ; 010   ; Unsigned Binary                                       ;
; h_back         ; 011   ; Unsigned Binary                                       ;
; v_video        ; 100   ; Unsigned Binary                                       ;
; v_front        ; 101   ; Unsigned Binary                                       ;
; v_sync         ; 110   ; Unsigned Binary                                       ;
; v_back         ; 111   ; Unsigned Binary                                       ;
+----------------+-------+-------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version
    Info: Processing started: Fri May 16 21:15:10 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga_colour_bar -c vga_colour_bar
Info: Found 1 design units, including 1 entities, in source file vga_colour_bar.v
    Info: Found entity 1: vga_colour_bar
Info: Elaborating entity "vga_colour_bar" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at vga_colour_bar.v(35): truncated value with size 32 to match size of target (11)
Warning (10230): Verilog HDL assignment warning at vga_colour_bar.v(43): truncated value with size 32 to match size of target (11)
Warning (10270): Verilog HDL Case Statement warning at vga_colour_bar.v(59): incomplete case statement has no default case item
Warning (10235): Verilog HDL Always Construct warning at vga_colour_bar.v(69): variable "h_state" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10270): Verilog HDL Case Statement warning at vga_colour_bar.v(69): incomplete case statement has no default case item
Warning (10230): Verilog HDL assignment warning at vga_colour_bar.v(90): truncated value with size 32 to match size of target (2)
Warning (10270): Verilog HDL Case Statement warning at vga_colour_bar.v(103): incomplete case statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at vga_colour_bar.v(92): inferring latch(es) for variable "colourx", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at vga_colour_bar.v(92): inferring latch(es) for variable "coloury", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at vga_colour_bar.v(92): inferring latch(es) for variable "colourz", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at vga_colour_bar.v(92): inferring latch(es) for variable "R", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at vga_colour_bar.v(92): inferring latch(es) for variable "G", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at vga_colour_bar.v(92): inferring latch(es) for variable "B", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "B[0]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "B[1]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "B[2]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "B[3]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "B[4]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "B[5]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "B[6]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "B[7]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "G[0]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "G[1]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "G[2]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "G[3]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "G[4]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "G[5]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "G[6]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "G[7]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "R[0]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "R[1]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "R[2]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "R[3]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "R[4]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "R[5]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "R[6]" at vga_colour_bar.v(103)
Info (10041): Inferred latch for "R[7]" at vga_colour_bar.v(103)
Warning: No clock transition on "h_state[2]~reg0" register due to stuck clock or clock enable
Warning: Reduced register "h_state[2]~reg0" with stuck clock_enable port to stuck value GND
Info: Power-up level of register "v_state[2]~reg0" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "v_state[2]~reg0" with stuck data_in port to stuck value VCC
Warning: No clock transition on "v_state[0]~reg0" register due to stuck clock or clock enable
Warning: Reduced register "v_state[0]~reg0" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "v_state[1]~reg0" register due to stuck clock or clock enable
Warning: Reduced register "v_state[1]~reg0" with stuck clock_enable port to stuck value GND
Info: Duplicate LATCH primitives merged into single LATCH primitive
    Info: Duplicate LATCH primitive "R[1]$latch" merged with LATCH primitive "R[0]$latch"
    Info: Duplicate LATCH primitive "R[2]$latch" merged with LATCH primitive "R[0]$latch"
    Info: Duplicate LATCH primitive "R[3]$latch" merged with LATCH primitive "R[0]$latch"
    Info: Duplicate LATCH primitive "R[4]$latch" merged with LATCH primitive "R[0]$latch"
    Info: Duplicate LATCH primitive "R[5]$latch" merged with LATCH primitive "R[0]$latch"
    Info: Duplicate LATCH primitive "R[6]$latch" merged with LATCH primitive "R[0]$latch"
    Info: Duplicate LATCH primitive "R[7]$latch" merged with LATCH primitive "R[0]$latch"
    Info: Duplicate LATCH primitive "G[1]$latch" merged with LATCH primitive "G[0]$latch"
    Info: Duplicate LATCH primitive "G[2]$latch" merged with LATCH primitive "G[0]$latch"
    Info: Duplicate LATCH primitive "G[3]$latch" merged with LATCH primitive "G[0]$latch"
    Info: Duplicate LATCH primitive "G[4]$latch" merged with LATCH primitive "G[0]$latch"
    Info: Duplicate LATCH primitive "G[5]$latch" merged with LATCH primitive "G[0]$latch"
    Info: Duplicate LATCH primitive "G[6]$latch" merged with LATCH primitive "G[0]$latch"
    Info: Duplicate LATCH primitive "G[7]$latch" merged with LATCH primitive "G[0]$latch"
    Info: Duplicate LATCH primitive "B[1]$latch" merged with LATCH primitive "B[0]$latch"
    Info: Duplicate LATCH primitive "B[2]$latch" merged with LATCH primitive "B[0]$latch"
    Info: Duplicate LATCH primitive "B[3]$latch" merged with LATCH primitive "B[0]$latch"
    Info: Duplicate LATCH primitive "B[4]$latch" merged with LATCH primitive "B[0]$latch"
    Info: Duplicate LATCH primitive "B[5]$latch" merged with LATCH primitive "B[0]$latch"
    Info: Duplicate LATCH primitive "B[6]$latch" merged with LATCH primitive "B[0]$latch"
    Info: Duplicate LATCH primitive "B[7]$latch" merged with LATCH primitive "B[0]$latch"
Warning: Latch R[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal mode[0]~reg0
Warning: Latch G[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal mode[0]~reg0
Warning: Latch B[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal mode[0]~reg0
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "h_state[2]" stuck at GND
    Warning: Pin "v_state[0]" stuck at GND
    Warning: Pin "v_state[1]" stuck at GND
    Warning: Pin "v_state[2]" stuck at VCC
Info: Implemented 109 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 58 output pins
    Info: Implemented 48 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 31 warnings
    Info: Allocated 140 megabytes of memory during processing
    Info: Processing ended: Fri May 16 21:15:16 2008
    Info: Elapsed time: 00:00:06