vga_colour_bar.fit.qmsg

用verilog hdl实现的VGA显示彩条信号

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "2.551 ns register register " "Info: Estimated most critical path is register to register delay of 2.551 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns v_cnt\[3\]~reg0 1 REG LAB_X17_Y18 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X17_Y18; Fanout = 5; REG Node = 'v_cnt\[3\]~reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { v_cnt[3]~reg0 } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v" 40 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.505 ns) + CELL(0.272 ns) 0.777 ns Equal7~102 2 COMB LAB_X18_Y19 1 " "Info: 2: + IC(0.505 ns) + CELL(0.272 ns) = 0.777 ns; Loc. = LAB_X18_Y19; Fanout = 1; COMB Node = 'Equal7~102'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.777 ns" { v_cnt[3]~reg0 Equal7~102 } "NODE_NAME" } } { "vga_colour_bar.v" "" { Text "E:/VGA_1024×768×85_彩条信号/vga_colour_bar.v"