vga_colour_bar.v

用verilog hdl实现的VGA显示彩条信号

module vga_colour_bar(rst,clk,enmode,mode,R,G,B,h_state,v_state,Hsync,Vsync,Cblank,valid,h_cnt,v_cnt);
 input rst;
 input clk;
 input enmode;
 output [1:0] mode;
 output [7:0] R,G,B;
 output [2:0] h_state,v_state;
 output Hsync;
 output Vsync;
 output Cblank;
 output valid;
 output [10:0] h_cnt;
 output [10:0] v_cnt;
 reg [1:0] mode;
 reg [7:0] R,G,B;
 wire Hsync; 
 wire Vsync;
 wire h_blank,v_blank;
 wire Cblank;
 wire valid;
 reg [10:0] h_cnt;
 reg [10:0] v_cnt;
 reg [2:0] h_state,next_h_state;
 reg [2:0] v_state,next_v_state;
 reg [2:0] colourx,coloury,colourz;
 parameter h_video=3'b000,h_front=3'b001,h_sync=3'b010,h_back=3'b011;
 parameter v_video=3'b100,v_front=3'b101,v_sync=3'b110,v_back=3'b111;

 always @(posedge clk or negedge rst)
   if(!rst)
     h_cnt<=0;
   else if (h_cnt==1375)
     h_cnt<=0;
   else
     h_cnt<=h_cnt+1;

 always @(posedge clk or negedge rst)
   if(!rst)
     v_cnt<=0;
   else if (v_cnt==806)
     v_cnt<=0;
   else if (h_cnt==1375)
     v_cnt<=v_cnt+1;

 always @(posedge clk or negedge rst)
   if(!rst)
     begin
         h_state<=h_video;
         v_state<=v_video;
     end
   else
     begin
         h_state<=next_h_state;
         v_state<=next_v_state;
     end

 always @(h_state or h_cnt)
  begin next_h_state=h_state;
   case(h_state)
    h_video: if(h_cnt==1023) next_h_state=h_front;
    h_front: if(h_cnt==1087) next_h_state=h_sync;
    h_sync:  if(h_cnt==1199) next_h_state=h_back;
    h_back:  if(h_cnt==1375) next_h_state=h_video;
   endcase
  end

 always @(v_state or v_cnt)
  begin next_v_state=v_state;
   case(h_state)
    v_video: if(v_cnt==767) next_v_state=v_front;
    v_front: if(v_cnt==768) next_v_state=v_sync;
    v_sync:  if(v_cnt==771) next_v_state=v_back;
    v_back:  if(v_cnt==806) next_v_state=v_video;
   endcase
  end

 assign Hsync=(!((h_cnt>=1087)&&(h_cnt<=1199)));
 assign Vsync=(!((v_cnt>=768)&&(v_cnt<=771)));
 assign h_blank=(h_cnt>=0)&&(h_cnt<=1023);
 assign v_blank=(v_cnt>=0)&&(v_cnt<=767);
 assign Cblank=h_blank & v_blank;
 assign valid=((h_cnt>=0)&&(h_cnt<=1023)&&(v_cnt>=0)&&(v_cnt<=767));

 always @(negedge rst or posedge enmode)
   if(!rst)
     mode<=0;
   else if (mode==2)
     mode<=0;
   else if (enmode)
     mode<=mode+1;

 always @(mode or Cblank or h_cnt or v_cnt)
   if(!Cblank)
     begin
       colourx=3'b000;
       coloury=3'b000;
       colourz=3'b000;
       R=8'H00;
       G=8'H00;
       B=8'H00;
     end
   else
     case(mode)
       0: begin coloury=3'b000;colourz=3'b000;
          if(h_cnt[4:0]<=3)       begin colourx=3'b111;R=8'HFF;G=8'HFF;B=8'HFF;end
          else if(h_cnt[4:0]<=7)  begin colourx=3'b110;R=8'HFF;G=8'HFF;B=8'H00;end
          else if(h_cnt[4:0]<=11) begin colourx=3'b101;R=8'H00;G=8'HFF;B=8'HFF;end
          else if(h_cnt[4:0]<=15) begin colourx=3'b100;R=8'H00;G=8'HFF;B=8'H00;end
          else if(h_cnt[4:0]<=19) begin colourx=3'b011;R=8'HFF;G=8'H00;B=8'HFF;end
          else if(h_cnt[4:0]<=23) begin colourx=3'b010;R=8'HFF;G=8'H00;B=8'H00;end
          else if(h_cnt[4:0]<=27) begin colourx=3'b001;R=8'H00;G=8'H00;B=8'HFF;end
          else                    begin colourx=3'b000;R=8'H00;G=8'H00;B=8'H00;end
          end
       1: begin colourx=3'b000;colourz=3'b000;
          if(v_cnt[4:0]<=3)       begin coloury=3'b111;R=8'HFF;G=8'HFF;B=8'HFF;end
          else if(v_cnt[4:0]<=7)  begin coloury=3'b110;R=8'HFF;G=8'HFF;B=8'H00;end
          else if(v_cnt[4:0]<=11) begin coloury=3'b101;R=8'H00;G=8'HFF;B=8'HFF;end
          else if(v_cnt[4:0]<=15) begin coloury=3'b100;R=8'H00;G=8'HFF;B=8'H00;end
          else if(v_cnt[4:0]<=19) begin coloury=3'b011;R=8'HFF;G=8'H00;B=8'HFF;end
          else if(v_cnt[4:0]<=23) begin coloury=3'b010;R=8'HFF;G=8'H00;B=8'H00;end
          else if(v_cnt[4:0]<=27) begin coloury=3'b001;R=8'H00;G=8'H00;B=8'HFF;end
          else                    begin coloury=3'b000;R=8'H00;G=8'H00;B=8'H00;end
          end
       2: begin
            if(h_cnt[4:0]<=3)       colourx=3'b111;
            else if(h_cnt[4:0]<=7)  colourx=3'b110;
            else if(h_cnt[4:0]<=11) colourx=3'b101;
            else if(h_cnt[4:0]<=15) colourx=3'b100;
            else if(h_cnt[4:0]<=19) colourx=3'b011;
            else if(h_cnt[4:0]<=23) colourx=3'b010;
            else if(h_cnt[4:0]<=27) colourx=3'b001;
            else                    colourx=3'b000;

            if(v_cnt[4:0]<=3)       coloury=3'b111;
            else if(v_cnt[4:0]<=7)  coloury=3'b110;
            else if(v_cnt[4:0]<=11) coloury=3'b101;
            else if(v_cnt[4:0]<=15) coloury=3'b100;
            else if(v_cnt[4:0]<=19) coloury=3'b011;
            else if(v_cnt[4:0]<=23) coloury=3'b010;
            else if(v_cnt[4:0]<=27) coloury=3'b001;
            else                    coloury=3'b000;

            colourz=colourx | coloury;

            if(colourz==3'b111)
              begin
                R=8'HFF;
                G=8'HFF;
                B=8'HFF;
              end
            else if(colourz==3'b110)
              begin
                R=8'HFF;
                G=8'HFF;
                B=8'H00;
              end
            else if(colourz==3'b101)
              begin
                R=8'H00;
                G=8'HFF;
                B=8'HFF;
              end
            else if(colourz==3'b100)
              begin
                R=8'H00;
                G=8'HFF;
                B=8'H00;
              end
            else if(colourz==3'b011)
              begin
                R=8'HFF;
                G=8'H00;
                B=8'HFF;
              end
            else if(colourz==3'b010)
              begin
                R=8'HFF;
                G=8'H00;
                B=8'H00;
              end
            else if(colourz==3'b001)
              begin
                R=8'H00;
                G=8'H00;
                B=8'HFF;
              end
            else if(colourz==3'b000)
              begin
                R=8'H00;
                G=8'H00;
                B=8'H00;
              end
          end
     endcase
endmodule