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用ISE中各种工具设计“运动计时表”.加深对FPGA/CPLD设计流程的理解

    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i3> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i3> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i2> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i2> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i2> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i1> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i1> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i1> in unit <outs3>.
Entity <outs3> analyzed. Unit <outs3> generated.

Analyzing Entity <stmach_v> (Architecture <behavior>).
Entity <stmach_v> analyzed. Unit <stmach_v> generated.

Analyzing Entity <cb4ce_mxilinx_cnt60> (Architecture <schematic>).
    Set user-defined property "U_SET =  I_Q0_0" for instance <i_q0> in unit <cb4ce_mxilinx_cnt60>.
    Set user-defined property "U_SET =  I_Q1_1" for instance <i_q1> in unit <cb4ce_mxilinx_cnt60>.
    Set user-defined property "U_SET =  I_Q2_2" for instance <i_q2> in unit <cb4ce_mxilinx_cnt60>.
    Set user-defined property "U_SET =  I_Q3_3" for instance <i_q3> in unit <cb4ce_mxilinx_cnt60>.
Entity <cb4ce_mxilinx_cnt60> analyzed. Unit <cb4ce_mxilinx_cnt60> generated.

Analyzing Entity <cd4ce_mxilinx_cnt60> (Architecture <schematic>).
    Set user-defined property "INIT =  0" for instance <i_q0> in unit <cd4ce_mxilinx_cnt60>.
    Set user-defined property "INIT =  0" for instance <i_q1> in unit <cd4ce_mxilinx_cnt60>.
    Set user-defined property "INIT =  0" for instance <i_q2> in unit <cd4ce_mxilinx_cnt60>.
    Set user-defined property "INIT =  0" for instance <i_q3> in unit <cd4ce_mxilinx_cnt60>.
Entity <cd4ce_mxilinx_cnt60> analyzed. Unit <cd4ce_mxilinx_cnt60> generated.

Analyzing Entity <ftce_mxilinx_cnt60> (Architecture <schematic>).
    Set user-defined property "INIT =  0" for instance <i_36_35> in unit <ftce_mxilinx_cnt60>.
    Set user-defined property "RLOC =  X0Y0" for instance <i_36_35> in unit <ftce_mxilinx_cnt60>.
Entity <ftce_mxilinx_cnt60> analyzed. Unit <ftce_mxilinx_cnt60> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ftce_mxilinx_cnt60>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf.
Unit <ftce_mxilinx_cnt60> synthesized.


Synthesizing Unit <cd4ce_mxilinx_cnt60>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf.
Unit <cd4ce_mxilinx_cnt60> synthesized.


Synthesizing Unit <cb4ce_mxilinx_cnt60>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf.
Unit <cb4ce_mxilinx_cnt60> synthesized.


Synthesizing Unit <stmach_v>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/STMACH_V.vhd.
    Found finite state machine <FSM_0> for signal <sreg>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 11                                             |
    | Inputs             | 1                                              |
    | Outputs            | 2                                              |
    | Reset type         | asynchronous                                   |
    | Encoding           | automatic                                      |
    | State register     | d  flip-flops                                  |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 Finite State Machine(s).
Unit <stmach_v> synthesized.


Synthesizing Unit <outs3>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/outs3.vhf.
Unit <outs3> synthesized.


Synthesizing Unit <hex2led>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/hex2led.vhd.
    Found 16x7-bit ROM for signal <led>.
    Summary:
	inferred   1 ROM(s).
Unit <hex2led> synthesized.


Synthesizing Unit <decode>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/decode.vhd.
    Found 16x10-bit ROM for signal <one_hot>.
    Summary:
	inferred   1 ROM(s).
Unit <decode> synthesized.


Synthesizing Unit <dcm1>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd.
Unit <dcm1> synthesized.


Synthesizing Unit <cnt60>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf.
Unit <cnt60> synthesized.


Synthesizing Unit <stopwatch>.
    Related source file is J:/projects/ISE/ISEexamples/wtut_sc/stopwatch.vhf.
Unit <stopwatch> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 3
  16x7-bit ROM                     : 2
  16x10-bit ROM                    : 1

=========================================================================

Optimizing FSM <FSM_0> with One-Hot encoding and d flip-flops.
=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Launcher: "tenths.ngo" is up to date.
Loading core <tenths> for timing and area information for instance <tenths_t>.

Library "J:/eda/Xilinx/data/librtl.xst" Consulted

Optimizing unit <stopwatch> ...

Optimizing unit <outs3> ...

Optimizing unit <stmach_v> ...

Optimizing unit <cd4ce_mxilinx_cnt60> ...

Optimizing unit <ftce_mxilinx_cnt60> ...

Optimizing unit <cb4ce_mxilinx_cnt60> ...

Mapping all equations...
Loading device for application Xst from file '2v40.nph' in environment J:/eda/Xilinx.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block stopwatch, actual ratio is 11.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v40fg256-5 

 Number of Slices:                      29  out of    256    11%  
 Number of Slice Flip Flops:            20  out of    512     3%  
 Number of 4 input LUTs:                42  out of    512     8%  
 Number of bonded IOBs:                 27  out of     88    30%  
 Number of GCLKs:                        1  out of     16     6%  
 Number of DCMs:                         1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | dcm1_t_dcm_inst:clk0   | 20    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 6.981ns (Maximum Frequency: 143.246MHz)
   Minimum input arrival time before clock: 2.736ns
   Maximum output required time after clock: 8.543ns
   Maximum combinational path delay: No path found

=========================================================================

Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -quiet -dd j:\projects\ise\iseexamples\wtut_sc/_ngo -i
-insert_keep_hierarchy -p xc2v40-fg256-5 stopwatch.ngc stopwatch.ngd 

Reading NGO file "J:/projects/ISE/ISEexamples/wtut_sc/stopwatch.ngc" ...
Reading component libraries for design expansion...
Launcher: Executing edif2ngd -noa "tenths.edn"
"j:\projects\ise\iseexamples\wtut_sc\_ngo\tenths.ngo"
INFO:NgdBuild - Release 5.1i - edif2ngd F.23
INFO:NgdBuild - Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
Writing the design to "j:/projects/ise/iseexamples/wtut_sc/_ngo/tenths.ngo"...
Loading design module "j:\projects\ise\iseexamples\wtut_sc\_ngo\tenths.ngo"...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:454 - logical net 'cnt60_t_xlxi_2/ceo' has no load
WARNING:NgdBuild:454 - logical net 'cnt60_t_xlxi_3/ceo' has no load

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   2

Writing NGD file "stopwatch.ngd" ...

Writing NGDBUILD log file "stopwatch.bld"...

NGDBUILD done.

Completed process "Translate".



Started process "Map".

Using target part "2v40fg256-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
   Number of errors:      0
   Number of warnings:    1
   Number of Slices:                   31 out of     256   12%
   Number of Slices containing
      unrelated logic:                  0 out of      31    0%
   Number of Slice Flip Flops:         20 out of     512    3%
   Number of 4 input LUTs:             53 out of     512   10%
   Number of bonded IOBs:              27 out of      88   30%
   Number of GCLKs:                     1 out of      16    6%
   Number of DCMs:                      1 out of       4   25%
   Number of RPM macros:            1
Total equivalent gate count for design:  7,502
Additional JTAG gate count for IOBs:  1,296
Peak Memory Usage:  54 MB

Mapping completed.
See MAP report file "stopwatch_map.mrp" for details.

Completed process "Map".

Mapping Module stopwatch . . .
MAP command line:
map -quiet -p xc2v40-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o stopwatch_map.ncd stopwatch.ngd stopwatch.pcf
Mapping Module stopwatch: DONE



Started process "Place & Route".

Release 5.1i - Par F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.




Constraints file: stopwatch.pcf

Loading device database for application par from file "stopwatch_map.ncd".
   "stopwatch" is an NCD, version 2.37, device xc2v40, package fg256, speed -5
Loading device for application par from file '2v40.nph' in environment
J:/eda/Xilinx.
The STEPPING level for this design is 1.
Device speed data version:  ADVANCED 1.110 2002-07-03.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External IOBs            27 out of 88     30%
      Number of LOCed External IOBs    1 out of 27      3%

   Number of SLICEs                   31 out of 256    12%

   Number of BUFGMUXs                  1 out of 16      6%
   Number of DCMs                      1 out of 4      25%



Overall effort level (-ol):   2 (set by user)
Placer effort level (-pl):    2 (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    2 (set by user)


Phase 1.1
Phase 1.1 (Checksum:989788) REAL time: 2 secs 

Phase 3.23
....................................
Phase 3.23 (Checksum:989682) REAL time: 2 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 2 secs 

Phase 6.8
.....
Phase 6.8 (Checksum:9910d7) REAL time: 2 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 2 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 2 secs 

Phase 9.24
Phase 9.24 (Checksum:55d4a77) REAL time: 2 secs 

Writing design to file stopwatch.ncd.

Total REAL time to placer completion: 2 secs 
Total CPU time to placer completion: 1 secs 


Starting Router          REAL time: 2 secs 

Phase 1: 266 unrouted;       REAL time: 2 secs 

Phase 2: 241 unrouted;       REAL time: 2 secs 

Phase 3: 71 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Finished Router          REAL time: 2 secs 

Total REAL time to router completion: 2 secs 
Total CPU time to router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Max Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|           clk_int          |  Global  |   15   |  0.011     |  0.570      |
+----------------------------+----------+--------+------------+-------------+


All signals are completely routed.

Total REAL time to par completion: 2 secs 
Total CPU time to par completion: 1 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file stopwatch.ncd.


PAR done.

Completed process "Place & Route".


Started process "Generate Post-Place & Route