__projnav.log

用ISE中各种工具设计“运动计时表”.加深对FPGA/CPLD设计流程的理解

Phase 4.3 (Checksum:26259fc) REAL time: 2 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 2 secs 

Phase 6.8
...
Phase 6.8 (Checksum:990add) REAL time: 2 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 2 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 2 secs 

Phase 9.24
Phase 9.24 (Checksum:55d4a77) REAL time: 2 secs 

Writing design to file stopwatch.ncd.

Total REAL time to placer completion: 2 secs 
Total CPU time to placer completion: 1 secs 


Starting Router          REAL time: 2 secs 

Phase 1: 266 unrouted;       REAL time: 2 secs 

Phase 2: 241 unrouted;       REAL time: 2 secs 

Phase 3: 65 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Finished Router          REAL time: 2 secs 

Total REAL time to router completion: 2 secs 
Total CPU time to router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Max Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|           clk_int          |  Global  |   15   |  0.004     |  0.561      |
+----------------------------+----------+--------+------------+-------------+


All signals are completely routed.

Total REAL time to par completion: 2 secs 
Total CPU time to par completion: 1 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file stopwatch.ncd.


PAR done.

Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Loading device database for application trce.exe from file "stopwatch.ncd".
   "stopwatch" is an NCD, version 2.37, device xc2v40, package fg256, speed -5
Loading device for application trce.exe from file '2v40.nph' in environment
J:/eda/Xilinx.
The STEPPING level for this design is 1.

Analysis completed Tue Nov 12 10:44:18 2002
--------------------------------------------------------------------------------

Generating Report ...


Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module stopwatch . . .
PAR command line: par -w -ol 2 -t 1 stopwatch_map.ncd stopwatch.ncd stopwatch.pcf
PAR completed successfully




Started process "Generate Programming File".

Release 5.1i - Bitgen F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Loading device database for application Bitgen from file "stopwatch.ncd".
   "stopwatch" is an NCD, version 2.37, device xc2v40, package fg256, speed -5
Loading device for application Bitgen from file '2v40.nph' in environment
J:/eda/Xilinx.
The STEPPING level for this design is 1.
Opened constraints file stopwatch.pcf.

Tue Nov 12 10:44:19 2002

Running DRC.
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "stopwatch.bit".
Bitstream generation is complete.

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------

Release 5.1i - sch2jhd F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.


Project Navigator Auto-Make Log File
-------------------------------------

deleting stopwatch.vhf
deleting stopwatch.cmd_log
deleting cnt60.vhf
deleting cnt60.cmd_log
deleting DCM1.vhd
deleting outs3.vhf
deleting outs3.cmd_log
deleting stopwatch.syr
deleting stopwatch.ngr
deleting stopwatch.prj
deleting stopwatch.sprj
deleting stopwatch.ana
deleting stopwatch.stx
deleting stopwatch.cmd_log
deleting stopwatch.vhf
deleting stopwatch.cmd_log
deleting stopwatch.syr
deleting stopwatch.ngr
deleting stopwatch.prj
deleting stopwatch.sprj
deleting stopwatch.ana
deleting stopwatch.stx
deleting stopwatch.cmd_log
deleting stopwatch.ngc
deleting __projnav/ngdbuild.err
deleting __projnav/ednTOngd_tcl.rsp
deleting j:\projects\ise\iseexamples\wtut_sc/_ngo
deleting stopwatch.ngd
deleting stopwatch_ngdbuild.nav
deleting stopwatch.bld
deleting .untf
deleting stopwatch.cmd_log
deleting stopwatch.nc1
deleting stopwatch.mrp
deleting stopwatch.pcf
deleting stopwatch.ngm
deleting stopwatch_map.ngm
deleting stopwatch.mdf
deleting stopwatch_map.ncd
deleting __projnav/map.log
deleting stopwatch.cmd_log
deleting __projnav/ncdTOtwr_tcl.rsp
deleting __projnav/posttrc.log
deleting stopwatch.twr
deleting stopwatch.twx
deleting stopwatch.tsi
deleting stopwatch.cmd_log
deleting __projnav/nc1TOncd_tcl.rsp
deleting stopwatch.ncd
deleting stopwatch.par
deleting stopwatch.pad
deleting stopwatch.dly
deleting stopwatch.xpi
deleting stopwatch.grf
deleting stopwatch.itr
deleting stopwatch_last_par.ncd
deleting __projnav/par.log
deleting stopwatch.cmd_log
deleting __projnav/stopwatch_ncdTOut_tcl.rsp
deleting __projnav/bitgen.rsp
deleting bitgen.ut
deleting stopwatch.ut
deleting stopwatch.bgn
deleting stopwatch.rbt
deleting stopwatch.ll
deleting stopwatch.msk
deleting stopwatch.drc
deleting stopwatch.nky
deleting stopwatch.bit
deleting stopwatch.bin
deleting stopwatch.isc
deleting stopwatch.cmd_log
deleting __projnav/stopwatch._sprj
deleting stopwatch.sprj
deleting stopwatch.sprj
deleting __projnav/stopwatch._prj
deleting stopwatch.prj
deleting stopwatch.prj
deleting __projnav/stopwatch.xst
deleting ./xst
deleting __projnav/stopwatch._sprj
deleting stopwatch.sprj
deleting stopwatch.sprj
deleting __projnav/stopwatch._prj
deleting stopwatch.prj
deleting stopwatch.prj
deleting __projnav/stopwatch.xst
deleting ./xst
deleting __projnav/wtut_sc.gfl
deleting __projnav/wtut_sc_flowplus.gfl
Finished cleaning up project


Project Navigator Auto-Make Log File
-------------------------------------

Release 5.1i - sch2jhd F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.


Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 5.1i - sch2vhdl F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.

Completed process "View VHDL Functional Model".



Started process "View VHDL Functional Model".

Release 5.1i - sch2vhdl F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.

Completed process "View VHDL Functional Model".



Started process "View HDL Source".

Release 5.1i - xaw2vhdl F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Completed process "View HDL Source".



Started process "View VHDL Functional Model".

Release 5.1i - sch2vhdl F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.

Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf in Library work.
Entity <ftce_mxilinx_cnt60> (Architecture <schematic>) compiled.
Entity <cb4ce_mxilinx_cnt60> (Architecture <schematic>) compiled.
Entity <cd4ce_mxilinx_cnt60> (Architecture <schematic>) compiled.
Entity <cnt60> (Architecture <schematic>) compiled.
Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd in Library work.
Entity <dcm1> (Architecture <struct>) compiled.
Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/decode.vhd in Library work.
Entity <decode> (Architecture <behavioral>) compiled.
Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/hex2led.vhd in Library work.
Entity <hex2led> (Architecture <behavioral>) compiled.
Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/outs3.vhf in Library work.
Entity <outs3> (Architecture <schematic>) compiled.
Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/STMACH_V.vhd in Library work.
Entity <stmach_v> (Architecture <behavior>) compiled.
Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/stopwatch.vhf in Library work.
Entity <stopwatch> (Architecture <schematic>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================

Analyzing Entity <stopwatch> (Architecture <schematic>).
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <xlxi_11> in unit <stopwatch>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <xlxi_10> in unit <stopwatch>.
    Set user-defined property "LOC =  A5" for instance <xlxi_10> in unit <stopwatch>.
WARNING:Xst:766 - J:/projects/ISE/ISEexamples/wtut_sc/stopwatch.vhf line 160: Generating a Black Box for component <tenths>.
Entity <stopwatch> analyzed. Unit <stopwatch> generated.

Analyzing Entity <cnt60> (Architecture <schematic>).
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf line 459: Unconnected output port 'ceo' of component 'cb4ce_mxilinx_cnt60'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf line 459: Unconnected output port 'tc' of component 'cb4ce_mxilinx_cnt60'.
    Set user-defined property "U_SET =  XLXI_3_5" for instance <xlxi_3> in unit <cnt60>.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf line 464: Unconnected output port 'ceo' of component 'cd4ce_mxilinx_cnt60'.
    Set user-defined property "U_SET =  XLXI_2_4" for instance <xlxi_2> in unit <cnt60>.
Entity <cnt60> analyzed. Unit <cnt60> generated.

Analyzing Entity <dcm1> (Architecture <struct>).
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'clk90' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'clk180' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'clk270' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'clkdv' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'clk2x' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'clk2x180' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'clkfx' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'clkfx180' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'status' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'locked' of component 'dcm'.
WARNING:Xst:753 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Unconnected output port 'psdone' of component 'dcm'.
WARNING:Xst:766 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 110: Generating a Black Box for component <dcm>.
    Set user-defined property "CLK_FEEDBACK =  1X" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "CLKDV_DIVIDE =  2.000000" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "CLKFX_DIVIDE =  1" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "CLKIN_DIVIDE_BY_2 =  false" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "CLKIN_PERIOD =  20.000000" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "DUTY_CYCLE_CORRECTION =  true" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "PHASE_SHIFT =  0" for instance <dcm_inst> in unit <dcm1>.
    Set user-defined property "STARTUP_WAIT =  true" for instance <dcm_inst> in unit <dcm1>.
WARNING:Xst:766 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 137: Generating a Black Box for component <ibufg>.
WARNING:Xst:766 - J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd line 142: Generating a Black Box for component <bufg>.
Entity <dcm1> analyzed. Unit <dcm1> generated.

Analyzing Entity <decode> (Architecture <behavioral>).
Entity <decode> analyzed. Unit <decode> generated.

Analyzing Entity <hex2led> (Architecture <behavioral>).
Entity <hex2led> analyzed. Unit <hex2led> generated.

Analyzing Entity <outs3> (Architecture <schematic>).
    Set user-defined property "DRIVE =  12" for instance <i10> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i10> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i10> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i9> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i9> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i9> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i8> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i8> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i8> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i7> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i7> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i7> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i6> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i6> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i6> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i5> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i5> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i5> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i4> in unit <outs3>.
    Set user-defined property "IOSTANDARD =  LVTTL" for instance <i4> in unit <outs3>.
    Set user-defined property "slew =  SLOW" for instance <i4> in unit <outs3>.
    Set user-defined property "DRIVE =  12" for instance <i3> in unit <outs3>.