📄 __projnav.log

📁 用ISE中各种工具设计“运动计时表”.加深对FPGA/CPLD设计流程的理解
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Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - sch2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - sch2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - sch2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - sch2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - sch2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - sch2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - sch2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - sch2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - sch2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - sch2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - sch2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - sch2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - sch2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - sch2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 5.1i - sch2vhdl F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".
Started process "View VHDL Functional Model".Release 5.1i - sch2vhdl F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".
Started process "View HDL Source".Release 5.1i - xaw2vhdl F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.Completed process "View HDL Source".
Started process "View VHDL Functional Model".Release 5.1i - sch2vhdl F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".


Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf in Library work.Entity <ftce_mxilinx_cnt60> (Architecture <schematic>) compiled.Entity <cb4ce_mxilinx_cnt60> (Architecture <schematic>) compiled.Entity <cd4ce_mxilinx_cnt60> (Architecture <schematic>) compiled.Entity <cnt60> (Architecture <schematic>) compiled.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd in Library work.Entity <dcm1> (Architecture <struct>) compiled.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/decode.vhd in Library work.Entity <decode> (Architecture <behavioral>) compiled.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/hex2led.vhd in Library work.Architecture behavioral of Entity hex2led is up to date.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/outs3.vhf in Library work.Entity <outs3> (Architecture <schematic>) compiled.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/STMACH_V.vhd in Library work.Architecture behavior of Entity stmach_v is up to date.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/stopwatch.vhf in Library work.ERROR:HDLParsers:1202 - J:/projects/ISE/ISEexamples/wtut_sc/stopwatch.vhf Line 163. Redeclaration of symbol tenths.--> Total memory usage is 41840 kilobytesError: XST failedReason: Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------

deleting __projnav/decode_jhdparse_tcl.rspdeleting __projnav/stopwatch_tb_jhdparse_tcl.rspdeleting __projnav/coregenApp_tcl.rspdeleting __projnav/coregen.crpdeleting coregen.prjdeleting coregen.findeleting __projnav/STMACH_V_jhdparse_tcl.rspdeleting DCM1.spldeleting __projnav/hex2led_jhdparse_tcl.rspdeleting __projnav/hex2led_jhdparse_tcl.rspdeleting hex2led.stxdeleting __projnav/tb.rspdeleting hex2led.spldeleting automake.errdeleting __projnav/tb.rspdeleting stmach_v.spldeleting automake.errdeleting stopwatch.vhfdeleting stopwatch.cmd_logdeleting cnt60.vhfdeleting cnt60.cmd_logdeleting DCM1.vhddeleting outs3.vhfdeleting outs3.cmd_logdeleting stopwatch.syrdeleting stopwatch.ngrdeleting stopwatch.prjdeleting stopwatch.sprjdeleting stopwatch.anadeleting stopwatch.stxdeleting stopwatch.cmd_logdeleting __projnav/hex2led._sprjdeleting hex2led.sprjdeleting hex2led.sprjdeleting hex2led.sprjdeleting __projnav/xst_sprjTOstx_tcl.rspdeleting __projnav/hex2led.xstdeleting xstdeleting __projnav/stopwatch._sprjdeleting stopwatch.sprjdeleting stopwatch.sprjdeleting __projnav/stopwatch._prjdeleting stopwatch.prjdeleting stopwatch.prjdeleting __projnav/stopwatch.xstdeleting ./xstdeleting __projnav/wtut_sc.gfldeleting __projnav/wtut_sc_flowplus.gflFinished cleaning up project

Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 5.1i - sch2vhdl F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".
Started process "View VHDL Functional Model".Release 5.1i - sch2vhdl F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".
Started process "View HDL Source".Release 5.1i - xaw2vhdl F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.Completed process "View HDL Source".
Started process "View VHDL Functional Model".Release 5.1i - sch2vhdl F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".


Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf in Library work.Entity <ftce_mxilinx_cnt60> (Architecture <schematic>) compiled.Entity <cb4ce_mxilinx_cnt60> (Architecture <schematic>) compiled.Entity <cd4ce_mxilinx_cnt60> (Architecture <schematic>) compiled.Entity <cnt60> (Architecture <schematic>) compiled.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd in Library work.Entity <dcm1> (Architecture <struct>) compiled.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/decode.vhd in Library work.Entity <decode> (Architecture <behavioral>) compiled.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/hex2led.vhd in Library work.Entity <hex2led> (Architecture <behavioral>) compiled.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/outs3.vhf in Library work.Entity <outs3> (Architecture <schematic>) compiled.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/STMACH_V.vhd in Library work.Entity <stmach_v> (Architecture <behavior>) compiled.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/stopwatch.vhf in Library work.ERROR:HDLParsers:1202 - J:/projects/ISE/ISEexamples/wtut_sc/stopwatch.vhf Line 163. Redeclaration of symbol tenths.--> Total memory usage is 41840 kilobytesError: XST failedReason: Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------

Release 5.1i - sch2jhd F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Project Navigator Auto-Make Log File-------------------------------------

Started process "View VHDL Functional Model".Release 5.1i - sch2vhdl F.23Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".


Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/cnt60.vhf in Library work.Architecture schematic of Entity ftce_mxilinx_cnt60 is up to date.Architecture schematic of Entity cb4ce_mxilinx_cnt60 is up to date.Architecture schematic of Entity cd4ce_mxilinx_cnt60 is up to date.Architecture schematic of Entity cnt60 is up to date.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/DCM1.vhd in Library work.Architecture struct of Entity dcm1 is up to date.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/decode.vhd in Library work.Architecture behavioral of Entity decode is up to date.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/hex2led.vhd in Library work.Architecture behavioral of Entity hex2led is up to date.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/outs3.vhf in Library work.Architecture schematic of Entity outs3 is up to date.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/STMACH_V.vhd in Library work.Architecture behavior of Entity stmach_v is up to date.Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/stopwatch.vhf in Library work.Entity <stopwatch> (Architecture <schematic>) compiled.=========================================================================*                            HDL Analysis                               *=========================================================================Analyzing Entity <stopwatch> (Architecture <schematic>).    Set user-defined property "IOSTANDARD =  LVTTL" for instance <xlxi_11> in unit <stopwatch>.    Set user-defined property "IOSTANDARD =  LVTTL" for instance <xlxi_10> in unit <stopwatch>.    Set user-defined property "LOC =  A5" for instance <xlxi_10> in unit <stopwatch>.WARNING:Xst:766 - J:/projects/ISE/ISEexamples/wtut_sc/stopwatch.vhf line 160: Generating a Black Box for component <tenths>.
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