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用ISE中各种工具设计“运动计时表”.加深对FPGA/CPLD设计流程的理解

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Release 5.1i - sch2jhd F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Release 5.1i - sch2jhd F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    decode.vhd
Scanning    decode.vhd
Writing decode.jhd.

JHDPARSE complete -    0 errors,    0 warnings.




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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Release 5.1i - sch2jhd F.23
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Started process "Create Schematic Symbol".

Release 5.1i - sch2sym F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Completed process "Create Schematic Symbol".



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Release 5.1i - sch2jhd F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.


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Release 5.1i - sch2jhd F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.


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JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Writing tenths.jhd.

JHDPARSE complete -    0 errors,    0 warnings.


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JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    STMACH_V.vhd
Scanning    STMACH_V.vhd
Writing STMACH_V.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



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Release 5.1i - xaw2jhd F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.


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Release 5.1i - xaw2jhd F.23
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Started process "Create Schematic Symbol".

Release 5.1i - xaw2spl F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Release 5.1i - spl2sym F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Completed process "Create Schematic Symbol".



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Release 5.1i - sch2jhd F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.


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Release 5.1i - sch2jhd F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.


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JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    hex2led.vhd
Scanning    hex2led.vhd
Writing hex2led.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



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JHDPARSE - VHDL/Verilog Parser.
ISE 5.1i Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Scanning    hex2led.vhd
Scanning    hex2led.vhd
Writing hex2led.jhd.

JHDPARSE complete -    0 errors,    0 warnings.



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Started process "Check Syntax".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/hex2led.vhd in Library work.
Entity <hex2led> (Architecture <behavioral>) compiled.

Completed process "Check Syntax".



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Started process "Create Schematic Symbol".

Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/hex2led.vhd in Library
work.
Entity <hex2led> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 5.1i - spl2sym F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Completed process "Create Schematic Symbol".



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Release 5.1i - sch2jhd F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.


Project Navigator Auto-Make Log File
-------------------------------------

Release 5.1i - sch2jhd F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.


Project Navigator Auto-Make Log File
-------------------------------------

Release 5.1i - sch2jhd F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.


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Started process "Create Schematic Symbol".

Compiling vhdl file J:/projects/ISE/ISEexamples/wtut_sc/STMACH_V.vhd in Library
work.
Entity <stmach_v> (Architecture <behavior>) compiled.
tdtfi(vhdl) completed successfully.


Release 5.1i - spl2sym F.23
Copyright (c) 1995-2002 Xilinx, Inc.  All rights reserved.

Completed process "Create Schematic Symbol".



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-------------------------------------

Release 5.1i - sch2jhd F.23