readme.txt

来自「用ISE中各种工具设计“运动计时表”.加深对FPGA/CPLD设计流程的理解」· 文本 代码 · 共 39 行

WATCH_SC is a top level VHDL type project of a Stop Watch. 

DESIGN TYPE:
        Foundation ISE 

CONTROLS 
Inputs:
* CLK -System clock for the Watch design.
* STRTSTOP -Starts and stops the stoopwatch. This is an active-low signal 
            which acts like the start/stop button on a runner's stop-watch.
* RESET -Resets the stopwatch to 00.0 after it has been stopped.

Outputs:
* TENSOUT[6:0] -7-bit bus which represents the Tens digit of the stopwatch 
                value. This bus is in 7-segment display format to be viewable 
                on the 7-segment LED display. 
* ONESOUT[6:0] -similar to TENSOUT bus above, but represents the Ones digit 
                of the stopwatch value.
* TENTHSOUT[9:0] -10-bit bus which represents the Tenths digit of the stopwatch 
                  value. This bus is one-hot encoded.

DESCRIPTION:
* STMACH_A or STMACH_V -State Machine macro. This module uses the VSS 
                        StateCAD Editor to enter and implement the state machine. 
* CNT60 -Schematic-based module which counts from 0 to 59, decimal. This macro 
         has two 4-bit outputs, which represent the 'ones' and 'tens' digits of 
         the decimal values, respectively.
* TENTHS -A LogiBLOX 10-bit, one-hot encoded counter. This macro outputs the 
          'tenths' digit of the watch value as a 10-bit one-hot encoded value.
* HEX2LED -HDL-based macro. This macro decodes the ones and tens digit values 
           from hexadecimal to 7-segment display format.
* OUTS1, OUTS2, OUTS3 -Schematic-based macros which define the external output 
                       pin assignments for TENSOUT, ONESOUT, and TENTHSOUT 
                       output buses.

SIMULATION:
Behavioural and RTL Simulation done using VHDL Testbench (watch_tb.vhd).