stopwatch_translate.vhd

用ISE中各种工具设计“运动计时表”.加深对FPGA/CPLD设计流程的理解

-- Xilinx Vhdl produced by program ngd2vhdl F.23
-- Command: -quiet -rpw 100 -tpw 0 -ar Structure -xon false -w -log __projnav/ngd2vhdl.log stopwatch.ngd stopwatch_translate.vhd 
-- Input file: stopwatch.ngd
-- Output file: stopwatch_translate.vhd
-- Design name: stopwatch
-- Xilinx: J:/eda/Xilinx
-- # of Entities: 2
-- Device: 2v40fg256-5

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

-- Model for  TOC (Tristate-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity TOC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 0 ns);
  port(O : out std_ulogic := '0');
  attribute VITAL_LEVEL0 of TOC : entity is TRUE;
end TOC;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    O <= '1';
    if (WIDTH <= 0 ns) then
       O <= '0';
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end TOC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity tenths is
  port (
    ce : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    ainit : in STD_LOGIC := 'X'; 
    q_thresh0 : out STD_LOGIC; 
    GSR : in STD_LOGIC := 'X'; 
    q : out STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
end tenths;

architecture Structure of tenths is
  signal N0 : STD_LOGIC; 
  signal N6 : STD_LOGIC; 
  signal CE_0 : STD_LOGIC; 
  signal N7 : STD_LOGIC; 
  signal N5 : STD_LOGIC; 
  signal N4 : STD_LOGIC; 
  signal N3 : STD_LOGIC; 
  signal N2 : STD_LOGIC; 
  signal N46 : STD_LOGIC; 
  signal CLK_1 : STD_LOGIC; 
  signal N84 : STD_LOGIC; 
  signal Q_THRESH0_2 : STD_LOGIC; 
  signal N97 : STD_LOGIC; 
  signal N98 : STD_LOGIC; 
  signal N100 : STD_LOGIC; 
  signal N143 : STD_LOGIC; 
  signal AINIT_3 : STD_LOGIC; 
  signal N103 : STD_LOGIC; 
  signal N105 : STD_LOGIC; 
  signal N160 : STD_LOGIC; 
  signal N108 : STD_LOGIC; 
  signal N110 : STD_LOGIC; 
  signal N177 : STD_LOGIC; 
  signal N113 : STD_LOGIC; 
  signal N194 : STD_LOGIC; 
  signal BU28_GSR_OR : STD_LOGIC; 
  signal BU36_GSR_OR : STD_LOGIC; 
  signal BU44_GSR_OR : STD_LOGIC; 
  signal BU51_GSR_OR : STD_LOGIC; 
  signal NLW_VCC_O_UNCONNECTED : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal NlwRenamedSig_OI_Q : STD_LOGIC_VECTOR ( 3 downto 0 ); 
begin
  CE_0 <= ce;
  CLK_1 <= clk;
  AINIT_3 <= ainit;
  q(0) <= NlwRenamedSig_OI_Q(0);
  q(1) <= NlwRenamedSig_OI_Q(1);
  q(2) <= NlwRenamedSig_OI_Q(2);
  q(3) <= NlwRenamedSig_OI_Q(3);
  q_thresh0 <= Q_THRESH0_2;
  VCC : X_ONE
    port map (
      O => NLW_VCC_O_UNCONNECTED
    );
  GND_4 : X_ZERO
    port map (
      O => N0
    );
  BU3 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => N6,
      ADR1 => CE_0,
      ADR2 => N0,
      ADR3 => N0,
      O => N7
    );
  BU9 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => N5,
      ADR1 => N4,
      ADR2 => N3,
      ADR3 => N2,
      O => N46
    );
  BU10 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CE => CE_0,
      CLK => CLK_1,
      I => N46,
      O => N6,
      SET => GND,
      RST => GSR
    );
  BU16 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => N5,
      ADR1 => N4,
      ADR2 => N3,
      ADR3 => N2,
      O => N84
    );
  BU17 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CE => CE_0,
      CLK => CLK_1,
      I => N84,
      O => Q_THRESH0_2,
      SET => GND,
      RST => GSR
    );
  BU20 : X_LUT4
    generic map(
      INIT => X"eeee"
    )
    port map (
      ADR0 => CE_0,
      ADR1 => N7,
      ADR2 => N0,
      ADR3 => N0,
      O => N97
    );
  BU22 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => NlwRenamedSig_OI_Q(0),
      ADR1 => N0,
      ADR2 => N0,
      ADR3 => N0,
      O => N98
    );
  BU23 : X_MUX2
    port map (
      IB => N0,
      IA => NlwRenamedSig_OI_Q(0),
      O => N100,
      SEL => N98
    );
  BU24 : X_XOR2
    port map (
      I0 => N0,
      I1 => N98,
      O => N2
    );
  BU27 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => N2,
      ADR1 => N7,
      ADR2 => N0,
      ADR3 => N0,
      O => N143
    );
  BU28 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      SET => BU28_GSR_OR,
      CE => N97,
      CLK => CLK_1,
      I => N143,
      O => NlwRenamedSig_OI_Q(0),
      RST => GND
    );
  BU30 : X_LUT4
    generic map(
      INIT => X"aaaa"
    )
    port map (
      ADR0 => NlwRenamedSig_OI_Q(1),
      ADR1 => N0,
      ADR2 => N0,
      ADR3 => N0,
      O => N103
    );
  BU31 : X_MUX2
    port map (
      IB => N100,
      IA => NlwRenamedSig_OI_Q(1),
      O => N105,
      SEL => N103
    );
  BU32 : X_XOR2
    port map (
      I0 => N100,
      I1 => N103,
      O => N3
    );
  BU35 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => N3,
      ADR1 => N7,
      ADR2 => N0,
      ADR3 => N0,
      O => N160
    );
  BU36 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CE => N97,
      CLK => CLK_1,
      I => N160,
      O => NlwRenamedSig_OI_Q(1),
      RST => BU36_GSR_OR,
      SET => GND
    );
  BU38 : X_LUT4
    generic map(
      INIT => X"aaaa"
    )
    port map (
      ADR0 => NlwRenamedSig_OI_Q(2),
      ADR1 => N0,
      ADR2 => N0,
      ADR3 => N0,
      O => N108
    );
  BU39 : X_MUX2
    port map (
      IB => N105,
      IA => NlwRenamedSig_OI_Q(2),
      O => N110,
      SEL => N108
    );
  BU40 : X_XOR2
    port map (
      I0 => N105,
      I1 => N108,
      O => N4
    );
  BU43 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => N4,
      ADR1 => N7,
      ADR2 => N0,
      ADR3 => N0,
      O => N177
    );
  BU44 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CE => N97,
      CLK => CLK_1,
      I => N177,
      O => NlwRenamedSig_OI_Q(2),
      RST => BU44_GSR_OR,
      SET => GND
    );
  BU46 : X_LUT4
    generic map(
      INIT => X"aaaa"
    )
    port map (
      ADR0 => NlwRenamedSig_OI_Q(3),
      ADR1 => N0,
      ADR2 => N0,
      ADR3 => N0,
      O => N113
    );
  BU47 : X_XOR2
    port map (
      I0 => N110,
      I1 => N113,
      O => N5
    );
  BU50 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => N5,
      ADR1 => N7,
      ADR2 => N0,
      ADR3 => N0,
      O => N194
    );
  BU51 : X_FF
    generic map(
      XON => FALSE
    )
    port map (
      CE => N97,
      CLK => CLK_1,
      I => N194,
      O => NlwRenamedSig_OI_Q(3),
      RST => BU51_GSR_OR,
      SET => GND
    );
  BU28_GSR_OR_5 : X_OR2
    port map (
      I0 => AINIT_3,
      I1 => GSR,
      O => BU28_GSR_OR
    );
  BU36_GSR_OR_6 : X_OR2
    port map (
      I0 => AINIT_3,
      I1 => GSR,
      O => BU36_GSR_OR
    );
  BU44_GSR_OR_7 : X_OR2
    port map (
      I0 => AINIT_3,
      I1 => GSR,
      O => BU44_GSR_OR
    );
  BU51_GSR_OR_8 : X_OR2
    port map (
      I0 => AINIT_3,
      I1 => GSR,
      O => BU51_GSR_OR
    );
  NlwBlock_tenths_t_GND : X_ZERO
    port map (
      O => GND
    );
end Structure;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity stopwatch is
  port (
    clk : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    starstop : in STD_LOGIC := 'X'; 
    onesout : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    tensout : out STD_LOGIC_VECTOR ( 6 downto 0 ); 
    tenthsout : out STD_LOGIC_VECTOR ( 9 downto 0 ) 
  );
end stopwatch;

architecture Structure of stopwatch is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  component TOC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 0 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  component tenths
    port (
      ce : in STD_LOGIC := 'X'; 
      clk : in STD_LOGIC := 'X'; 
      ainit : in STD_LOGIC := 'X'; 
      q_thresh0 : out STD_LOGIC; 
      GSR : in STD_LOGIC := 'X'; 
      q : out STD_LOGIC_VECTOR ( 3 downto 0 ) 
    );
  end component;
  signal xlxn_105 : STD_LOGIC; 
  signal xlxn_2 : STD_LOGIC; 
  signal xlxn_3 : STD_LOGIC; 
  signal xlxn_5 : STD_LOGIC; 
  signal xlxn_95 : STD_LOGIC; 
  signal clk_int : STD_LOGIC; 
  signal clken_int : STD_LOGIC; 
  signal stmach_t_sreg_ffd1 : STD_LOGIC; 
  signal onesout_6_obuf : STD_LOGIC; 
  signal onesout_5_obuf : STD_LOGIC; 
  signal onesout_4_obuf : STD_LOGIC; 
  signal onesout_3_obuf : STD_LOGIC; 
  signal onesout_2_obuf : STD_LOGIC; 
  signal onesout_1_obuf : STD_LOGIC; 
  signal onesout_0_obuf : STD_LOGIC; 
  signal tensout_6_obuf : STD_LOGIC; 
  signal tensout_5_obuf : STD_LOGIC; 
  signal tensout_4_obuf : STD_LOGIC; 
  signal tensout_3_obuf : STD_LOGIC; 
  signal tensout_2_obuf : STD_LOGIC; 
  signal tensout_1_obuf : STD_LOGIC; 
  signal tensout_0_obuf : STD_LOGIC; 
  signal dcm1_t_clkin_ibufg : STD_LOGIC; 
  signal n579 : STD_LOGIC; 
  signal dcm1_t_clk0_buf : STD_LOGIC; 
  signal cnt60_t_xlxn_15 : STD_LOGIC;