decode.v

来自「用ISE中各种工具设计“运动计时表”.加深对FPGA/CPLD设计流程的理解」· Verilog 代码 · 共 26 行

module decode (binary,one_hot);
input [3:0] binary;
output[9:0] one_hot;

reg [9:0]  one_hot;

always @(binary)
begin
   case (binary)
	    4'b0001 : one_hot = 10'b0000000001;			//1 
	    4'b0010 : one_hot = 10'b0000000010;			//2
	    4'b0011 : one_hot = 10'b0000000100;			//3
	    4'b0100 : one_hot = 10'b0000001000;			//4
	    4'b0101 : one_hot = 10'b0000010000;			//5
	    4'b0110 : one_hot = 10'b0000100000;			//6
	    4'b0111 : one_hot = 10'b0001000000;			//7
	    4'b1000 : one_hot = 10'b0010000000;			//8
	    4'b1001 : one_hot = 10'b0100000000;			//9
	    4'b1010 : one_hot = 10'b1000000000;			//10
	    default : one_hot = 10'b0000000001;			//1 
	 endcase	       
end 


endmodule