syn_pro_stopwatch.sdc

用ISE中各种工具设计“运动计时表”.加深对FPGA/CPLD设计流程的理解

# Synplicity, Inc. constraint file
# J:\ISE\watch_sc\Synplify_Pro\Syn_Pro_stopwatch.sdc
# Written on Fri Dec 06 09:54:17 2002
# by Synplify Pro, 7.2         Scope Editor

#
# Clocks
#
define_clock           -virtual -name {clk}  -freq 100.000 -clockgroup default_clkgroup

#
# Inputs/Outputs
#
define_input_delay               -default -clock {clk} -route 2.00 -ref clk:r
define_output_delay              -default -clock {clk} -route 2.00 -ref clk:r
define_input_delay -disable      {clk}
define_output_delay -disable     {onesout[6:0]}
define_input_delay -disable      {reset}
define_input_delay -disable      {strstop}
define_output_delay -disable     {tensout[6:0]}
define_output_delay -disable     {tenthsout[9:0]}

#
# Registers
#
define_reg_input_delay           {XLXI_5.clkout} -route 5.00
define_reg_input_delay           {XLXI_5.clkout} -route 5.00

#
# Multicycle Path
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#
# False Path
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# Attributes
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# Compile Points
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# Other Constraints
#