main.tan.qmsg

这是一个用verilog语言设计的数字频率及的源代码

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW1 register gate_control:inst3\|wire_1 register gate_control:inst3\|wire_2 23.15 MHz 43.2 ns Internal " "Info: Clock \"SW1\" has Internal fmax of 23.15 MHz between source register \"gate_control:inst3\|wire_1\" and destination register \"gate_control:inst3\|wire_2\" (period= 43.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gate_control:inst3\|wire_1 1 REG LC193 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.600 ns) 6.000 ns gate_control:inst3\|wire_2 2 REG LC201 24 " "Info: 2: + IC(3.400 ns) + CELL(2.600 ns) = 6.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 43.33 % " "Info: Total cell delay = 2.600 ns ( 43.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.400 ns 56.67 % " "Info: Total interconnect delay = 3.400 ns ( 56.67 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.400ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-13.400 ns - Smallest " "Info: - Smallest clock skew is -13.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 destination 13.000 ns + Shortest register " "Info: + Shortest clock path from clock \"SW1\" to destination register is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW1 1 CLK PIN_145 18 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_145; Fanout = 18; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { SW1 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 248 -224 -56 264 "SW1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.800 ns) 7.100 ns gate_control:inst3\|fref~126 2 COMB LOOP LC205 4 " "Info: 2: + IC(0.000 ns) + CELL(6.800 ns) = 7.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.800 ns" { SW1 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 13.000 ns gate_control:inst3\|wire_2 3 REG LC201 24 " "Info: 3: + IC(3.000 ns) + CELL(2.900 ns) = 13.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 76.92 % " "Info: Total cell delay = 10.000 ns ( 76.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 23.08 % " "Info: Total interconnect delay = 3.000 ns ( 23.08 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW1 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW1 SW1~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.800ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW1 source 26.400 ns - Longest register " "Info: - Longest clock path from clock \"SW1\" to source register is 26.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW1 1 CLK PIN_145 18 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_145; Fanout = 18; CLK Node = 'SW1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { SW1 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 248 -224 -56 264 "SW1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(3.700 ns) 7.100 ns gate_control:inst3\|fref~120 2 COMB LC195 1 " "Info: 2: + IC(3.100 ns) + CELL(3.700 ns) = 7.100 ns; Loc. = LC195; Fanout = 1; COMB Node = 'gate_control:inst3\|fref~120'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.800 ns" { SW1 gate_control:inst3|fref~120 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.700 ns) 13.800 ns gate_control:inst3\|fref~114 3 COMB LC203 3 " "Info: 3: + IC(3.000 ns) + CELL(3.700 ns) = 13.800 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~120 gate_control:inst3|fref~114 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 20.500 ns gate_control:inst3\|fref~126 4 COMB LOOP LC205 4 " "Info: 4: + IC(0.000 ns) + CELL(6.700 ns) = 20.500 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Fl