📄 main.tan.qmsg

📁 这是一个用verilog语言设计的数字频率及的源代码
💻 QMSG
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{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "gate_control:inst3\|dp_s10hz~40 " "Info: Node \"gate_control:inst3\|dp_s10hz~40\"" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 12 -1 0 } }  } 0}  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 12 -1 0 } }  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clock " "Info: Assuming node \"Clock\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 352 -224 -56 368 "Clock" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Clock" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW2 " "Info: Assuming node \"SW2\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 264 -224 -56 280 "SW2" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW2" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW1 " "Info: Assuming node \"SW1\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 248 -224 -56 264 "SW1" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW1" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "SW0 " "Info: Assuming node \"SW0\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 232 -224 -56 248 "SW0" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "SW0" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "F_in " "Info: Assuming node \"F_in\" is an undefined clock" {  } { { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 56 -224 -56 72 "F_in" "" } } } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "F_in" } } } }  } 0}  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "10 " "Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "gate_control:inst3\|wire_2 " "Info: Detected ripple clock \"gate_control:inst3\|wire_2\" as buffer" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|wire_2" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "gate_control:inst3\|wire_1 " "Info: Detected ripple clock \"gate_control:inst3\|wire_1\" as buffer" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|wire_1" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "gate_control:inst3\|always0~44 " "Info: Detected gated clock \"gate_control:inst3\|always0~44\" as buffer" {  } { { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|always0~44" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "gate_control:inst3\|fref~126 " "Info: Detected gated clock \"gate_control:inst3\|fref~126\" as buffer" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|fref~126" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "gate_control:inst3\|fref~114 " "Info: Detected gated clock \"gate_control:inst3\|fref~114\" as buffer" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|fref~114" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "gate_control:inst3\|fref~120 " "Info: Detected gated clock \"gate_control:inst3\|fref~120\" as buffer" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "gate_control:inst3\|fref~120" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst1\|f1hz " "Info: Detected ripple clock \"fdiv:inst1\|f1hz\" as buffer" {  } { { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv:inst1\|f1hz" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst1\|f10hz " "Info: Detected ripple clock \"fdiv:inst1\|f10hz\" as buffer" {  } { { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv:inst1\|f10hz" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst1\|f100hz " "Info: Detected ripple clock \"fdiv:inst1\|f100hz\" as buffer" {  } { { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv:inst1\|f100hz" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "fdiv:inst1\|f1khz " "Info: Detected ripple clock \"fdiv:inst1\|f1khz\" as buffer" {  } { { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "fdiv:inst1\|f1khz" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clock register gate_control:inst3\|wire_1 register gate_control:inst3\|wire_2 17.12 MHz 58.4 ns Internal " "Info: Clock \"Clock\" has Internal fmax of 17.12 MHz between source register \"gate_control:inst3\|wire_1\" and destination register \"gate_control:inst3\|wire_2\" (period= 58.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gate_control:inst3\|wire_1 1 REG LC193 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.600 ns) 6.000 ns gate_control:inst3\|wire_2 2 REG LC201 24 " "Info: 2: + IC(3.400 ns) + CELL(2.600 ns) = 6.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 43.33 % " "Info: Total cell delay = 2.600 ns ( 43.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.400 ns 56.67 % " "Info: Total interconnect delay = 3.400 ns ( 56.67 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.400ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-21.000 ns - Smallest " "Info: - Smallest clock skew is -21.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock destination 31.000 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock\" to destination register is 31.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Clock 1 CLK PIN_181 33 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_181; Fanout = 33; CLK Node = 'Clock'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { Clock } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 352 -224 -56 368 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 4.200 ns fdiv:inst1\|f1khz 2 REG LC225 42 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 4.200 ns; Loc. = LC225; Fanout = 42; REG Node = 'fdiv:inst1\|f1khz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "1.400 ns" { Clock fdiv:inst1|f1khz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(4.000 ns) 11.500 ns fdiv:inst1\|f100hz 3 REG LC115 34 " "Info: 3: + IC(3.300 ns) + CELL(4.000 ns) = 11.500 ns; Loc. = LC115; Fanout = 34; REG Node = 'fdiv:inst1\|f100hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.300 ns" { fdiv:inst1|f1khz fdiv:inst1|f100hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(3.700 ns) 18.400 ns gate_control:inst3\|fref~114 4 COMB LC203 3 " "Info: 4: + IC(3.200 ns) + CELL(3.700 ns) = 18.400 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.900 ns" { fdiv:inst1|f100hz gate_control:inst3|fref~114 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 25.100 ns gate_control:inst3\|fref~126 5 COMB LOOP LC205 4 " "Info: 5: + IC(0.000 ns) + CELL(6.700 ns) = 25.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~114 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 31.000 ns gate_control:inst3\|wire_2 6 REG LC201 24 " "Info: 6: + IC(3.000 ns) + CELL(2.900 ns) = 31.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.500 ns 69.35 % " "Info: Total cell delay = 21.500 ns ( 69.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.500 ns 30.65 % " "Info: Total interconnect delay = 9.500 ns ( 30.65 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "31.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "31.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 3.700ns 6.700ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock source 52.000 ns - Longest register " "Info: - Longest clock path from clock \"Clock\" to source register is 52.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns Clock 1 CLK PIN_181 33 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_181; Fanout = 33; CLK Node = 'Clock'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { Clock } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 352 -224 -56 368 "Clock" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 4.200 ns fdiv:inst1\|f1khz 2 REG LC225 42 " "Info: 2: + IC(0.000 ns) + CELL(1.400 ns) = 4.200 ns; Loc. = LC225; Fanout = 42; REG Node = 'fdiv:inst1\|f1khz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "1.400 ns" { Clock fdiv:inst1|f1khz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(4.000 ns) 11.500 ns fdiv:inst1\|f100hz 3 REG LC115 34 " "Info: 3: + IC(3.300 ns) + CELL(4.000 ns) = 11.500 ns; Loc. = LC115; Fanout = 34; REG Node = 'fdiv:inst1\|f100hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.300 ns" { fdiv:inst1|f1khz fdiv:inst1|f100hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(4.000 ns) 18.700 ns fdiv:inst1\|f10hz 4 REG LC129 34 " "Info: 4: + IC(3.200 ns) + CELL(4.000 ns) = 18.700 ns; Loc. = LC129; Fanout = 34; REG Node = 'fdiv:inst1\|f10hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.200 ns" { fdiv:inst1|f100hz fdiv:inst1|f10hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(4.000 ns) 26.000 ns fdiv:inst1\|f1hz 5 REG LC145 1 " "Info: 5: + IC(3.300 ns) + CELL(4.000 ns) = 26.000 ns; Loc. = LC145; Fanout = 1; REG Node = 'fdiv:inst1\|f1hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "7.300 ns" { fdiv:inst1|f10hz fdiv:inst1|f1hz } "NODE_NAME" } "" } } { "fdiv.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/fdiv.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.700 ns) 32.700 ns gate_control:inst3\|fref~120 6 COMB LC195 1 " "Info: 6: + IC(3.000 ns) + CELL(3.700 ns) = 32.700 ns; Loc. = LC195; Fanout = 1; COMB Node = 'gate_control:inst3\|fref~120'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { fdiv:inst1|f1hz gate_control:inst3|fref~120 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(3.700 ns) 39.400 ns gate_control:inst3\|fref~114 7 COMB LC203 3 " "Info: 7: + IC(3.000 ns) + CELL(3.700 ns) = 39.400 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~120 gate_control:inst3|fref~114 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 46.100 ns gate_control:inst3\|fref~126 8 COMB LOOP LC205 4 " "Info: 8: + IC(0.000 ns) + CELL(6.700 ns) = 46.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~114 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 52.000 ns gate_control:inst3\|wire_1 9 REG LC193 114 " "Info: 9: + IC(3.000 ns) + CELL(2.900 ns) = 52.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "33.200 ns 63.85 % " "Info: Total cell delay = 33.200 ns ( 63.85 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "18.800 ns 36.15 % " "Info: Total interconnect delay = 18.800 ns ( 36.15 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "52.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "52.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 3.300ns 3.000ns 3.000ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 4.000ns 4.000ns 3.700ns 3.700ns 6.700ns 2.900ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "31.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "31.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 3.700ns 6.700ns 2.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "52.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "52.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 3.300ns 3.000ns 3.000ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 4.000ns 4.000ns 3.700ns 3.700ns 6.700ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.100 ns + " "Info: + Micro setup delay of destination is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.400ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "31.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "31.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 3.700ns 6.700ns 2.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "52.000 ns" { Clock fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "52.000 ns" { Clock Clock~out fdiv:inst1|f1khz fdiv:inst1|f100hz fdiv:inst1|f10hz fdiv:inst1|f1hz gate_control:inst3|fref~120 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 0.000ns 3.300ns 3.200ns 3.300ns 3.000ns 3.000ns 0.000ns 3.000ns } { 0.000ns 2.800ns 1.400ns 4.000ns 4.000ns 4.000ns 3.700ns 3.700ns 6.700ns 2.900ns } } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SW2 register gate_control:inst3\|wire_1 register gate_control:inst3\|wire_2 33.56 MHz 29.8 ns Internal " "Info: Clock \"SW2\" has Internal fmax of 33.56 MHz between source register \"gate_control:inst3\|wire_1\" and destination register \"gate_control:inst3\|wire_2\" (period= 29.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.000 ns + Longest register register " "Info: + Longest register to register delay is 6.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns gate_control:inst3\|wire_1 1 REG LC193 114 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.600 ns) 6.000 ns gate_control:inst3\|wire_2 2 REG LC201 24 " "Info: 2: + IC(3.400 ns) + CELL(2.600 ns) = 6.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 43.33 % " "Info: Total cell delay = 2.600 ns ( 43.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.400 ns 56.67 % " "Info: Total interconnect delay = 3.400 ns ( 56.67 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.400ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-6.700 ns - Smallest " "Info: - Smallest clock skew is -6.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 destination 13.000 ns + Shortest register " "Info: + Shortest clock path from clock \"SW2\" to destination register is 13.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW2 1 CLK PIN_129 21 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_129; Fanout = 21; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { SW2 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 264 -224 -56 280 "SW2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.800 ns) 7.100 ns gate_control:inst3\|fref~126 2 COMB LOOP LC205 4 " "Info: 2: + IC(0.000 ns) + CELL(6.800 ns) = 7.100 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.800 ns" { SW2 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 13.000 ns gate_control:inst3\|wire_2 3 REG LC201 24 " "Info: 3: + IC(3.000 ns) + CELL(2.900 ns) = 13.000 ns; Loc. = LC201; Fanout = 24; REG Node = 'gate_control:inst3\|wire_2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.000 ns 76.92 % " "Info: Total cell delay = 10.000 ns ( 76.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns 23.08 % " "Info: Total interconnect delay = 3.000 ns ( 23.08 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW2 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW2 SW2~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.800ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SW2 source 19.700 ns - Longest register " "Info: - Longest clock path from clock \"SW2\" to source register is 19.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns SW2 1 CLK PIN_129 21 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_129; Fanout = 21; CLK Node = 'SW2'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { SW2 } "NODE_NAME" } "" } } { "main.bdf" "" { Schematic "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/main.bdf" { { 264 -224 -56 280 "SW2" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.100 ns) + CELL(3.700 ns) 7.100 ns gate_control:inst3\|fref~114 2 COMB LC203 3 " "Info: 2: + IC(3.100 ns) + CELL(3.700 ns) = 7.100 ns; Loc. = LC203; Fanout = 3; COMB Node = 'gate_control:inst3\|fref~114'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.800 ns" { SW2 gate_control:inst3|fref~114 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.700 ns) 13.800 ns gate_control:inst3\|fref~126 3 COMB LOOP LC205 4 " "Info: 3: + IC(0.000 ns) + CELL(6.700 ns) = 13.800 ns; Loc. = LC205; Fanout = 4; COMB LOOP Node = 'gate_control:inst3\|fref~126'" { { "Info" "ITDB_PART_OF_SCC" "gate_control:inst3\|fref~126 LC205 " "Info: Loc. = LC205; Node \"gate_control:inst3\|fref~126\"" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "" { gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.700 ns" { gate_control:inst3|fref~114 gate_control:inst3|fref~126 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.900 ns) 19.700 ns gate_control:inst3\|wire_1 4 REG LC193 114 " "Info: 4: + IC(3.000 ns) + CELL(2.900 ns) = 19.700 ns; Loc. = LC193; Fanout = 114; REG Node = 'gate_control:inst3\|wire_1'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "5.900 ns" { gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.600 ns 69.04 % " "Info: Total cell delay = 13.600 ns ( 69.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.100 ns 30.96 % " "Info: Total interconnect delay = 6.100 ns ( 30.96 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "19.700 ns" { SW2 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "19.700 ns" { SW2 SW2~out gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.100ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 6.700ns 2.900ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW2 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW2 SW2~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.800ns 2.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "19.700 ns" { SW2 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "19.700 ns" { SW2 SW2~out gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.100ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 6.700ns 2.900ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.100 ns + " "Info: + Micro setup delay of destination is 1.100 ns" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 58 -1 0 } } { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 63 -1 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "6.000 ns" { gate_control:inst3|wire_1 gate_control:inst3|wire_2 } { 0.000ns 3.400ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "13.000 ns" { SW2 gate_control:inst3|fref~126 gate_control:inst3|wire_2 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "13.000 ns" { SW2 SW2~out gate_control:inst3|fref~126 gate_control:inst3|wire_2 } { 0.000ns 0.000ns 0.000ns 3.000ns } { 0.000ns 0.300ns 6.800ns 2.900ns } } } { "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main_cmp.qrpt" Compiler "main" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/db/main.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/" "" "19.700 ns" { SW2 gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "19.700 ns" { SW2 SW2~out gate_control:inst3|fref~114 gate_control:inst3|fref~126 gate_control:inst3|wire_1 } { 0.000ns 0.000ns 3.100ns 0.000ns 3.000ns } { 0.000ns 0.300ns 3.700ns 6.700ns 2.900ns } } }  } 0}
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