main.tan.rpt

这是一个用verilog语言设计的数字频率及的源代码

; Clock Setup: 'SW2'           ; N/A                                      ; None          ; 33.56 MHz ( period = 29.800 ns ) ; gate_control:inst3|wire_1                 ; gate_control:inst3|wire_2                 ; SW2        ; SW2      ; 0            ;
; Clock Setup: 'SW0'           ; N/A                                      ; None          ; 41.32 MHz ( period = 24.200 ns ) ; gate_control:inst3|wire_1                 ; gate_control:inst3|wire_2                 ; SW0        ; SW0      ; 0            ;
; Clock Setup: 'F_in'          ; N/A                                      ; None          ; 53.48 MHz ( period = 18.700 ns ) ; counter:inst|lpm_counter:Q1_rtl_2|dffs[1] ; counter:inst|lpm_counter:Q3_rtl_4|dffs[0] ; F_in       ; F_in     ; 0            ;
; Clock Hold: 'Clock'          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; gate_control:inst3|wire_1                 ; gate_control:inst3|wire_1                 ; Clock      ; Clock    ; 2            ;
; Clock Hold: 'SW1'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; gate_control:inst3|wire_1                 ; gate_control:inst3|wire_1                 ; SW1        ; SW1      ; 2            ;
; Clock Hold: 'SW2'            ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; gate_control:inst3|wire_1                 ; gate_control:inst3|wire_1                 ; SW2        ; SW2      ; 2            ;
; Total number of failed paths ;                                          ;               ;                                  ;                                           ;                                           ;            ;          ; 6            ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------------------+-------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM7256SQC208-7    ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minumum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Clock Analysis Only                                   ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Do Min/Max analysis using Rise/Fall delays            ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Use Clock Latency for PLL offset                      ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock           ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; SW2             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; SW1             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; SW0             ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
; F_in            ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'Clock'                                                                                                                                                                                                                                                                                ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------+--------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                       ; To                                         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+--------------------------------------------+--------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 17.12 MHz ( period = 58.400 ns )                    ; gate_control:inst3|wire_1                  ; gate_control:inst3|wire_2                  ; Clock      ; Clock    ; None                        ; None                      ; 6.000 ns                ;
; N/A                                     ; 34.72 MHz ( period = 28.800 ns )                    ; gate_control:inst3|wire_1                  ; gate_control:inst3|wire_1                  ; Clock      ; Clock    ; None                        ; None                      ; 5.600 ns                ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[3]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[2]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[27] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;
; N/A                                     ; 46.30 MHz ( period = 21.600 ns )                    ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[3]  ; fdiv:inst1|lpm_counter:cnt4_rtl_8|dffs[28] ; Clock      ; Clock    ; None                        ; None                      ; 19.400 ns               ;