_2sel1.vho

有用的verilog hdl实验用程序 配有截图

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

-- DATE "05/18/2008 09:11:22"

-- 
-- Device: Altera EP1K30TC144-3 Package TQFP144
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	\_2sel1\ IS
    PORT (
	in1 : IN std_logic;
	in2 : IN std_logic;
	sel : IN std_logic;
	\out\ : OUT std_logic
	);
END \_2sel1\;

ARCHITECTURE structure OF \_2sel1\ IS
SIGNAL GNDs : std_logic_vector(1024 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(1024 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_in1 : std_logic;
SIGNAL ww_in2 : std_logic;
SIGNAL ww_sel : std_logic;
SIGNAL \ww_out\ : std_logic;
SIGNAL \in1~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \in2~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \sel~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \out~4_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \out~4_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \out~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \in1~dataout\ : std_logic;
SIGNAL \in2~dataout\ : std_logic;
SIGNAL \sel~dataout\ : std_logic;
SIGNAL \out~4\ : std_logic;
COMPONENT flex10ke_lcell
PORT (
	dataa : IN STD_LOGIC;
	datab : IN STD_LOGIC;
	datac : IN STD_LOGIC;
	datad : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	aload : IN STD_LOGIC;
	clk : IN STD_LOGIC;
	cin : IN STD_LOGIC;
	cascin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	cout : OUT STD_LOGIC;
	cascout : OUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
	pathsel : IN STD_LOGIC_VECTOR(9 DOWNTO 0));
END COMPONENT;

COMPONENT flex10ke_io
PORT (
	datain : IN STD_LOGIC;
	clk : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	dataout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(10 DOWNTO 0));
END COMPONENT;


COMPONENT INV
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;
BEGIN

ww_in1 <= in1;
ww_in2 <= in2;
ww_sel <= sel;
\out\ <= \ww_out\;

gnd <= '0';
vcc <= '1';
GNDs <= (OTHERS => '0');
VCCs <= (OTHERS => '1');

\in1~I_modesel\ <= "01010000001";
\in2~I_modesel\ <= "01010000001";
\sel~I_modesel\ <= "01010000001";
\out~4_I_modesel\ <= "1000001";
\out~4_I_pathsel\ <= "0000001110";
\out~I_modesel\ <= "10010000010";

lcell_ff_enable_asynch_arcs : AND1
PORT MAP (
	 IN1 => GND,
	 Y => lcell_ff_enable_asynch_arcs_out);

-- atom is at PIN_19
\in1~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \in1~I_modesel\,
	dataout => \in1~dataout\,
	padio => ww_in1);

-- atom is at PIN_18
\in2~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \in2~I_modesel\,
	dataout => \in2~dataout\,
	padio => ww_in2);

-- atom is at PIN_17
\sel~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \sel~I_modesel\,
	dataout => \sel~dataout\,
	padio => ww_sel);

-- atom is at LC7_C20
\out~4_I\ : flex10ke_lcell
-- Equation(s):
-- \out~4\ = \sel~dataout\ & \in1~dataout\ # !\sel~dataout\ & (\in2~dataout\)

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "CCF0",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \out~4_I_pathsel\,
	dataa => VCC,
	datab => \in1~dataout\,
	datac => \in2~dataout\,
	datad => \sel~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \out~4_I_modesel\,
	combout => \out~4\);

-- atom is at PIN_29
\out~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \out~4\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \out~I_modesel\,
	padio => \ww_out\);
END structure;