_2sel1.vo

有用的verilog hdl实验用程序 配有截图

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

// DATE "05/18/2008 09:11:22"

// 
// Device: Altera EP1K30TC144-3 Package TQFP144
// 

// 
// This Verilog file should be used for Active-HDL (Verilog) only
// 

`timescale 1 ps/ 1 ps

module _2sel1 (
	in1,
	in2,
	sel,
	out);
input 	in1;
input 	in2;
input 	sel;
output 	out;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("_2sel1_v.sdo");
// synopsys translate_on

wire \in1~dataout ;
wire \in2~dataout ;
wire \sel~dataout ;
wire \out~4 ;


// atom is at PIN_19
flex10ke_io \in1~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\in1~dataout ),
	.padio(in1));
// synopsys translate_off
defparam \in1~I .feedback_mode = "from_pin";
defparam \in1~I .operation_mode = "input";
defparam \in1~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_18
flex10ke_io \in2~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\in2~dataout ),
	.padio(in2));
// synopsys translate_off
defparam \in2~I .feedback_mode = "from_pin";
defparam \in2~I .operation_mode = "input";
defparam \in2~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_17
flex10ke_io \sel~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\sel~dataout ),
	.padio(sel));
// synopsys translate_off
defparam \sel~I .feedback_mode = "from_pin";
defparam \sel~I .operation_mode = "input";
defparam \sel~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at LC7_C20
flex10ke_lcell \out~4_I (
// Equation(s):
// \out~4  = \sel~dataout  & \in1~dataout  # !\sel~dataout  & (\in2~dataout )

	.dataa(vcc),
	.datab(\in1~dataout ),
	.datac(\in2~dataout ),
	.datad(\sel~dataout ),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\out~4 ),
	.regout(),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \out~4_I .clock_enable_mode = "false";
defparam \out~4_I .lut_mask = "CCF0";
defparam \out~4_I .operation_mode = "normal";
defparam \out~4_I .output_mode = "comb_only";
defparam \out~4_I .packed_mode = "false";
// synopsys translate_on

// atom is at PIN_29
flex10ke_io \out~I (
	.datain(\out~4 ),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(),
	.padio(out));
// synopsys translate_off
defparam \out~I .feedback_mode = "none";
defparam \out~I .operation_mode = "output";
defparam \out~I .reg_source_mode = "none";
// synopsys translate_on

endmodule