_8bitfulladd.tan.qmsg

有用的verilog hdl实验用程序 配有截图

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 18 10:16:21 2008 " "Info: Processing started: Sun May 18 10:16:21 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off _8bitFullAdd -c _8bitFullAdd " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off _8bitFullAdd -c _8bitFullAdd" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "ina\[3\] cout 17.600 ns Longest " "Info: Longest tpd from source pin \"ina\[3\]\" to destination pin \"cout\" is 17.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns ina\[3\] 1 PIN PIN_48 2 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_48; Fanout = 2; PIN Node = 'ina\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ina[3] } "NODE_NAME" } } { "_8bitFullAdd.v" "" { Text "F:/_8bitFullAdd/_8bitFullAdd.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(0.700 ns) 7.800 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 2 COMB LC8_D31 2 " "Info: 2: + IC(2.200 ns) + CELL(0.700 ns) = 7.800 ns; Loc. = LC8_D31; Fanout = 2; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.900 ns" { ina[3] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.200 ns) 8.500 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 3 COMB LC1_D33 2 " "Info: 3: + IC(0.500 ns) + CELL(0.200 ns) = 8.500 ns; Loc. = LC1_D33; Fanout = 2; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.700 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.700 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 4 COMB LC2_D33 2 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 8.700 ns; Loc. = LC2_D33; Fanout = 2; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 8.900 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\] 5 COMB LC3_D33 2 " "Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 8.900 ns; Loc. = LC3_D33; Fanout = 2; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 9.100 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\] 6 COMB LC4_D33 1 " "Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 9.100 ns; Loc. = LC4_D33; Fanout = 1; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.200 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.400 ns) 10.500 ns lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[8\]~172 7 COMB LC5_D33 1 " "Info: 7: + IC(0.000 ns) + CELL(1.400 ns) = 10.500 ns; Loc. = LC5_D33; Fanout = 1; COMB Node = 'lpm_add_sub:Add0\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[8\]~172'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.400 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~172 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(6.300 ns) 17.600 ns cout 8 PIN PIN_141 0 " "Info: 8: + IC(0.800 ns) + CELL(6.300 ns) = 17.600 ns; Loc. = PIN_141; Fanout = 0; PIN Node = 'cout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.100 ns" { lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~172 cout } "NODE_NAME" } } { "_8bitFullAdd.v" "" { Text "F:/_8bitFullAdd/_8bitFullAdd.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.100 ns ( 80.11 % ) " "Info: Total cell delay = 14.100 ns ( 80.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.500 ns ( 19.89 % ) " "Info: Total interconnect delay = 3.500 ns ( 19.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "17.600 ns" { ina[3] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~172 cout } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "17.600 ns" { ina[3] ina[3]~out lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~172 cout } { 0.000ns 0.000ns 2.200ns 0.500ns 0.000ns 0.000ns 0.000ns 0.000ns 0.800ns } { 0.000ns 4.900ns 0.700ns 0.200ns 0.200ns 0.200ns 0.200ns 1.400ns 6.300ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 18 10:16:22 2008 " "Info: Processing ended: Sun May 18 10:16:22 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}