📄 _8bitfulladd_vhd.sdo
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// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//
// Device: Altera EP1K30TC144-3 Package TQFP144
//
//
// This SDF file should be used for PrimeTime (VHDL) only
//
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "\_8bitFullAdd\")
(DATE "05/18/2008 10:16:25")
(VENDOR "Altera")
(PROGRAM "Quartus II")
(VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version")
(DIVIDER .)
(TIMESCALE 1 ps)
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(IOPATH datab combout (1600:1600:1600) (1600:1600:1600))
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(IOPATH dataa cout (700:700:700) (700:700:700))
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(INSTANCE \\Add0\|adder\|result_node\|cs_buffer\[5\]\~I\\.lecomb)
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(IOPATH datab combout (1600:1600:1600) (1600:1600:1600))
(IOPATH cin combout (1400:1400:1400) (1400:1400:1400))
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(IOPATH datab combout (1600:1600:1600) (1600:1600:1600))
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(IOPATH datab cout (700:700:700) (700:700:700))
(IOPATH cin cout (200:200:200) (200:200:200))
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(INSTANCE \\ina\[0\]\~I\\.inst1)
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(INSTANCE \\sum\[7\]\~I\\.inst1)
(DELAY
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(IOPATH datain padio (6300:6300:6300) (6300:6300:6300))
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