_8bitfulladd.vho

有用的verilog hdl实验用程序 配有截图

--	clock_enable_mode => "false",
--	lut_mask => "96E8",
--	operation_mode => "arithmetic",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \Add0|adder|result_node|cs_buffer[3]~I_pathsel\,
	dataa => \ina[2]~dataout\,
	datab => \inb[2]~dataout\,
	datac => VCC,
	datad => VCC,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => \Add0|adder|result_node|cout[2]\,
	cascin => VCC,
	modesel => \Add0|adder|result_node|cs_buffer[3]~I_modesel\,
	combout => \Add0|adder|result_node|cs_buffer[3]\,
	cout => \Add0|adder|result_node|cout[3]\);

-- atom is at LC8_D31
\Add0|adder|result_node|cs_buffer[4]~I\ : flex10ke_lcell
-- Equation(s):
-- \Add0|adder|result_node|cs_buffer[4]\ = \ina[3]~dataout\ $ \inb[3]~dataout\ $ \Add0|adder|result_node|cout[3]\
-- \Add0|adder|result_node|cout[4]\ = CARRY(\ina[3]~dataout\ & (\inb[3]~dataout\ # \Add0|adder|result_node|cout[3]\) # !\ina[3]~dataout\ & \inb[3]~dataout\ & \Add0|adder|result_node|cout[3]\)

-- pragma translate_off
-- GENERIC MAP (
--	cin_used => "true",
--	clock_enable_mode => "false",
--	lut_mask => "96E8",
--	operation_mode => "arithmetic",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \Add0|adder|result_node|cs_buffer[4]~I_pathsel\,
	dataa => \ina[3]~dataout\,
	datab => \inb[3]~dataout\,
	datac => VCC,
	datad => VCC,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => \Add0|adder|result_node|cout[3]\,
	cascin => VCC,
	modesel => \Add0|adder|result_node|cs_buffer[4]~I_modesel\,
	combout => \Add0|adder|result_node|cs_buffer[4]\,
	cout => \Add0|adder|result_node|cout[4]\);

-- atom is at LC1_D33
\Add0|adder|result_node|cs_buffer[5]~I\ : flex10ke_lcell
-- Equation(s):
-- \Add0|adder|result_node|cs_buffer[5]\ = \ina[4]~dataout\ $ \inb[4]~dataout\ $ \Add0|adder|result_node|cout[4]\
-- \Add0|adder|result_node|cout[5]\ = CARRY(\ina[4]~dataout\ & (\inb[4]~dataout\ # \Add0|adder|result_node|cout[4]\) # !\ina[4]~dataout\ & \inb[4]~dataout\ & \Add0|adder|result_node|cout[4]\)

-- pragma translate_off
-- GENERIC MAP (
--	cin_used => "true",
--	clock_enable_mode => "false",
--	lut_mask => "96E8",
--	operation_mode => "arithmetic",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \Add0|adder|result_node|cs_buffer[5]~I_pathsel\,
	dataa => \ina[4]~dataout\,
	datab => \inb[4]~dataout\,
	datac => VCC,
	datad => VCC,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => \Add0|adder|result_node|cout[4]\,
	cascin => VCC,
	modesel => \Add0|adder|result_node|cs_buffer[5]~I_modesel\,
	combout => \Add0|adder|result_node|cs_buffer[5]\,
	cout => \Add0|adder|result_node|cout[5]\);

-- atom is at LC2_D33
\Add0|adder|result_node|cs_buffer[6]~I\ : flex10ke_lcell
-- Equation(s):
-- \Add0|adder|result_node|cs_buffer[6]\ = \ina[5]~dataout\ $ \inb[5]~dataout\ $ \Add0|adder|result_node|cout[5]\
-- \Add0|adder|result_node|cout[6]\ = CARRY(\ina[5]~dataout\ & (\inb[5]~dataout\ # \Add0|adder|result_node|cout[5]\) # !\ina[5]~dataout\ & \inb[5]~dataout\ & \Add0|adder|result_node|cout[5]\)

-- pragma translate_off
-- GENERIC MAP (
--	cin_used => "true",
--	clock_enable_mode => "false",
--	lut_mask => "96E8",
--	operation_mode => "arithmetic",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \Add0|adder|result_node|cs_buffer[6]~I_pathsel\,
	dataa => \ina[5]~dataout\,
	datab => \inb[5]~dataout\,
	datac => VCC,
	datad => VCC,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => \Add0|adder|result_node|cout[5]\,
	cascin => VCC,
	modesel => \Add0|adder|result_node|cs_buffer[6]~I_modesel\,
	combout => \Add0|adder|result_node|cs_buffer[6]\,
	cout => \Add0|adder|result_node|cout[6]\);

-- atom is at LC3_D33
\Add0|adder|result_node|cs_buffer[7]~I\ : flex10ke_lcell
-- Equation(s):
-- \Add0|adder|result_node|cs_buffer[7]\ = \ina[6]~dataout\ $ \inb[6]~dataout\ $ \Add0|adder|result_node|cout[6]\
-- \Add0|adder|result_node|cout[7]\ = CARRY(\ina[6]~dataout\ & (\inb[6]~dataout\ # \Add0|adder|result_node|cout[6]\) # !\ina[6]~dataout\ & \inb[6]~dataout\ & \Add0|adder|result_node|cout[6]\)

-- pragma translate_off
-- GENERIC MAP (
--	cin_used => "true",
--	clock_enable_mode => "false",
--	lut_mask => "96E8",
--	operation_mode => "arithmetic",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \Add0|adder|result_node|cs_buffer[7]~I_pathsel\,
	dataa => \ina[6]~dataout\,
	datab => \inb[6]~dataout\,
	datac => VCC,
	datad => VCC,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => \Add0|adder|result_node|cout[6]\,
	cascin => VCC,
	modesel => \Add0|adder|result_node|cs_buffer[7]~I_modesel\,
	combout => \Add0|adder|result_node|cs_buffer[7]\,
	cout => \Add0|adder|result_node|cout[7]\);

-- atom is at LC4_D33
\Add0|adder|result_node|cs_buffer[8]~I\ : flex10ke_lcell
-- Equation(s):
-- \Add0|adder|result_node|cs_buffer[8]\ = \ina[7]~dataout\ $ \inb[7]~dataout\ $ \Add0|adder|result_node|cout[7]\
-- \Add0|adder|result_node|cout[8]\ = CARRY(\ina[7]~dataout\ & (\inb[7]~dataout\ # \Add0|adder|result_node|cout[7]\) # !\ina[7]~dataout\ & \inb[7]~dataout\ & \Add0|adder|result_node|cout[7]\)

-- pragma translate_off
-- GENERIC MAP (
--	cin_used => "true",
--	clock_enable_mode => "false",
--	lut_mask => "96E8",
--	operation_mode => "arithmetic",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \Add0|adder|result_node|cs_buffer[8]~I_pathsel\,
	dataa => \ina[7]~dataout\,
	datab => \inb[7]~dataout\,
	datac => VCC,
	datad => VCC,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => \Add0|adder|result_node|cout[7]\,
	cascin => VCC,
	modesel => \Add0|adder|result_node|cs_buffer[8]~I_modesel\,
	combout => \Add0|adder|result_node|cs_buffer[8]\,
	cout => \Add0|adder|result_node|cout[8]\);

-- atom is at LC5_D33
\Add0|adder|result_node|cs_buffer[8]~172_I\ : flex10ke_lcell
-- Equation(s):
-- \Add0|adder|result_node|cs_buffer[8]~172\ = \Add0|adder|result_node|cout[8]\

-- pragma translate_off
-- GENERIC MAP (
--	cin_used => "true",
--	clock_enable_mode => "false",
--	lut_mask => "F0F0",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \Add0|adder|result_node|cs_buffer[8]~172_I_pathsel\,
	dataa => VCC,
	datab => VCC,
	datac => VCC,
	datad => VCC,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => \Add0|adder|result_node|cout[8]\,
	cascin => VCC,
	modesel => \Add0|adder|result_node|cs_buffer[8]~172_I_modesel\,
	combout => \Add0|adder|result_node|cs_buffer[8]~172\);

-- atom is at PIN_126
\ina[0]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \ina[0]~I_modesel\,
	dataout => \ina[0]~dataout\,
	padio => ww_ina(0));

-- atom is at PIN_54
\ina[1]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \ina[1]~I_modesel\,
	dataout => \ina[1]~dataout\,
	padio => ww_ina(1));

-- atom is at PIN_125
\ina[2]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \ina[2]~I_modesel\,
	dataout => \ina[2]~dataout\,
	padio => ww_ina(2));

-- atom is at PIN_48
\ina[3]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \ina[3]~I_modesel\,
	dataout => \ina[3]~dataout\,
	padio => ww_ina(3));

-- atom is at PIN_91
\ina[4]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \ina[4]~I_modesel\,
	dataout => \ina[4]~dataout\,
	padio => ww_ina(4));

-- atom is at PIN_92
\ina[5]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \ina[5]~I_modesel\,
	dataout => \ina[5]~dataout\,
	padio => ww_ina(5));

-- atom is at PIN_89
\ina[6]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \ina[6]~I_modesel\,
	dataout => \ina[6]~dataout\,
	padio => ww_ina(6));

-- atom is at PIN_42
\ina[7]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \ina[7]~I_modesel\,
	dataout => \ina[7]~dataout\,
	padio => ww_ina(7));

-- atom is at PIN_141
\cout~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \Add0|adder|result_node|cs_buffer[8]~172\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \cout~I_modesel\,
	padio => ww_cout);

-- atom is at PIN_41
\sum[0]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \Add0|adder|result_node|cs_buffer[1]\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \sum[0]~I_modesel\,
	padio => ww_sum(0));

-- atom is at PIN_140
\sum[1]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \Add0|adder|result_node|cs_buffer[2]\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \sum[1]~I_modesel\,
	padio => ww_sum(1));

-- atom is at PIN_23
\sum[2]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \Add0|adder|result_node|cs_buffer[3]\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \sum[2]~I_modesel\,
	padio => ww_sum(2));

-- atom is at PIN_88
\sum[3]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \Add0|adder|result_node|cs_buffer[4]\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \sum[3]~I_modesel\,
	padio => ww_sum(3));

-- atom is at PIN_19
\sum[4]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \Add0|adder|result_node|cs_buffer[5]\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \sum[4]~I_modesel\,
	padio => ww_sum(4));

-- atom is at PIN_20
\sum[5]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \Add0|adder|result_node|cs_buffer[6]\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \sum[5]~I_modesel\,
	padio => ww_sum(5));

-- atom is at PIN_142
\sum[6]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \Add0|adder|result_node|cs_buffer[7]\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \sum[6]~I_modesel\,
	padio => ww_sum(6));

-- atom is at PIN_39
\sum[7]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \Add0|adder|result_node|cs_buffer[8]\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \sum[7]~I_modesel\,
	padio => ww_sum(7));
END structure;