_8bitfulladd.vho

有用的verilog hdl实验用程序 配有截图

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

-- DATE "05/18/2008 10:16:25"

-- 
-- Device: Altera EP1K30TC144-3 Package TQFP144
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	\_8bitFullAdd\ IS
    PORT (
	cout : OUT std_logic;
	sum : OUT std_logic_vector(7 DOWNTO 0);
	ina : IN std_logic_vector(7 DOWNTO 0);
	inb : IN std_logic_vector(7 DOWNTO 0);
	cin : IN std_logic
	);
END \_8bitFullAdd\;

ARCHITECTURE structure OF \_8bitFullAdd\ IS
SIGNAL GNDs : std_logic_vector(1024 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(1024 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_cout : std_logic;
SIGNAL ww_sum : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_ina : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_inb : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_cin : std_logic;
SIGNAL \inb[7]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inb[6]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inb[5]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inb[4]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inb[3]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inb[2]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inb[1]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \inb[0]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \cin~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[0]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[0]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[1]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[1]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[2]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[2]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[3]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[3]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[4]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[4]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[5]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[5]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[6]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[6]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[7]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[7]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[8]~I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[8]~I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[8]~172_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[8]~172_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \ina[0]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \ina[1]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \ina[2]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \ina[3]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \ina[4]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \ina[5]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \ina[6]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \ina[7]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \cout~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \sum[0]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \sum[1]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \sum[2]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \sum[3]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \sum[4]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \sum[5]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \sum[6]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \sum[7]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \Add0|adder|result_node|cs_buffer[0]\ : std_logic;
SIGNAL \inb[7]~dataout\ : std_logic;
SIGNAL \inb[6]~dataout\ : std_logic;
SIGNAL \inb[5]~dataout\ : std_logic;
SIGNAL \inb[4]~dataout\ : std_logic;
SIGNAL \inb[3]~dataout\ : std_logic;
SIGNAL \inb[2]~dataout\ : std_logic;
SIGNAL \inb[1]~dataout\ : std_logic;
SIGNAL \inb[0]~dataout\ : std_logic;
SIGNAL \cin~dataout\ : std_logic;
SIGNAL \Add0|adder|result_node|cout[0]\ : std_logic;
SIGNAL \Add0|adder|result_node|cout[1]\ : std_logic;
SIGNAL \Add0|adder|result_node|cout[2]\ : std_logic;
SIGNAL \Add0|adder|result_node|cout[3]\ : std_logic;
SIGNAL \Add0|adder|result_node|cout[4]\ : std_logic;
SIGNAL \Add0|adder|result_node|cout[5]\ : std_logic;
SIGNAL \Add0|adder|result_node|cout[6]\ : std_logic;
SIGNAL \Add0|adder|result_node|cout[7]\ : std_logic;
SIGNAL \Add0|adder|result_node|cout[8]\ : std_logic;
SIGNAL \Add0|adder|result_node|cs_buffer[8]~172\ : std_logic;
SIGNAL \ina[0]~dataout\ : std_logic;
SIGNAL \Add0|adder|result_node|cs_buffer[1]\ : std_logic;
SIGNAL \ina[1]~dataout\ : std_logic;
SIGNAL \Add0|adder|result_node|cs_buffer[2]\ : std_logic;
SIGNAL \ina[2]~dataout\ : std_logic;
SIGNAL \Add0|adder|result_node|cs_buffer[3]\ : std_logic;
SIGNAL \ina[3]~dataout\ : std_logic;
SIGNAL \Add0|adder|result_node|cs_buffer[4]\ : std_logic;
SIGNAL \ina[4]~dataout\ : std_logic;
SIGNAL \Add0|adder|result_node|cs_buffer[5]\ : std_logic;
SIGNAL \ina[5]~dataout\ : std_logic;
SIGNAL \Add0|adder|result_node|cs_buffer[6]\ : std_logic;
SIGNAL \ina[6]~dataout\ : std_logic;
SIGNAL \Add0|adder|result_node|cs_buffer[7]\ : std_logic;
SIGNAL \ina[7]~dataout\ : std_logic;
SIGNAL \Add0|adder|result_node|cs_buffer[8]\ : std_logic;
COMPONENT flex10ke_lcell
PORT (
	dataa : IN STD_LOGIC;
	datab : IN STD_LOGIC;
	datac : IN STD_LOGIC;
	datad : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	aload : IN STD_LOGIC;
	clk : IN STD_LOGIC;
	cin : IN STD_LOGIC;
	cascin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	cout : OUT STD_LOGIC;
	cascout : OUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
	pathsel : IN STD_LOGIC_VECTOR(9 DOWNTO 0));
END COMPONENT;

COMPONENT flex10ke_io
PORT (
	datain : IN STD_LOGIC;
	clk : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	dataout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(10 DOWNTO 0));
END COMPONENT;


COMPONENT INV
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;
BEGIN

cout <= ww_cout;
sum <= ww_sum;
ww_ina <= ina;
ww_inb <= inb;
ww_cin <= cin;

gnd <= '0';
vcc <= '1';
GNDs <= (OTHERS => '0');
VCCs <= (OTHERS => '1');

\inb[7]~I_modesel\ <= "01010000001";
\inb[6]~I_modesel\ <= "01010000001";
\inb[5]~I_modesel\ <= "01010000001";
\inb[4]~I_modesel\ <= "01010000001";
\inb[3]~I_modesel\ <= "01010000001";
\inb[2]~I_modesel\ <= "01010000001";
\inb[1]~I_modesel\ <= "01010000001";
\inb[0]~I_modesel\ <= "01010000001";
\cin~I_modesel\ <= "01010000001";
\Add0|adder|result_node|cs_buffer[0]~I_modesel\ <= "1000010";
\Add0|adder|result_node|cs_buffer[0]~I_pathsel\ <= "0010000000";
\Add0|adder|result_node|cs_buffer[1]~I_modesel\ <= "1000010";
\Add0|adder|result_node|cs_buffer[1]~I_pathsel\ <= "0111010011";
\Add0|adder|result_node|cs_buffer[2]~I_modesel\ <= "1000010";
\Add0|adder|result_node|cs_buffer[2]~I_pathsel\ <= "0111010011";
\Add0|adder|result_node|cs_buffer[3]~I_modesel\ <= "1000010";
\Add0|adder|result_node|cs_buffer[3]~I_pathsel\ <= "0111010011";
\Add0|adder|result_node|cs_buffer[4]~I_modesel\ <= "1000010";
\Add0|adder|result_node|cs_buffer[4]~I_pathsel\ <= "0111010011";
\Add0|adder|result_node|cs_buffer[5]~I_modesel\ <= "1000010";
\Add0|adder|result_node|cs_buffer[5]~I_pathsel\ <= "0111010011";
\Add0|adder|result_node|cs_buffer[6]~I_modesel\ <= "1000010";
\Add0|adder|result_node|cs_buffer[6]~I_pathsel\ <= "0111010011";
\Add0|adder|result_node|cs_buffer[7]~I_modesel\ <= "1000010";
\Add0|adder|result_node|cs_buffer[7]~I_pathsel\ <= "0111010011";
\Add0|adder|result_node|cs_buffer[8]~I_modesel\ <= "1000010";
\Add0|adder|result_node|cs_buffer[8]~I_pathsel\ <= "0111010011";
\Add0|adder|result_node|cs_buffer[8]~172_I_modesel\ <= "1000001";
\Add0|adder|result_node|cs_buffer[8]~172_I_pathsel\ <= "0000010000";
\ina[0]~I_modesel\ <= "01010000001";
\ina[1]~I_modesel\ <= "01010000001";
\ina[2]~I_modesel\ <= "01010000001";
\ina[3]~I_modesel\ <= "01010000001";
\ina[4]~I_modesel\ <= "01010000001";
\ina[5]~I_modesel\ <= "01010000001";
\ina[6]~I_modesel\ <= "01010000001";
\ina[7]~I_modesel\ <= "01010000001";
\cout~I_modesel\ <= "10010000010";
\sum[0]~I_modesel\ <= "10010000010";
\sum[1]~I_modesel\ <= "10010000010";
\sum[2]~I_modesel\ <= "10010000010";
\sum[3]~I_modesel\ <= "10010000010";
\sum[4]~I_modesel\ <= "10010000010";
\sum[5]~I_modesel\ <= "10010000010";
\sum[6]~I_modesel\ <= "10010000010";
\sum[7]~I_modesel\ <= "10010000010";

lcell_ff_enable_asynch_arcs : AND1
PORT MAP (
	 IN1 => GND,
	 Y => lcell_ff_enable_asynch_arcs_out);

-- atom is at PIN_132
\inb[7]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \inb[7]~I_modesel\,
	dataout => \inb[7]~dataout\,
	padio => ww_inb(7));

-- atom is at PIN_143
\inb[6]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \inb[6]~I_modesel\,
	dataout => \inb[6]~dataout\,
	padio => ww_inb(6));

-- atom is at PIN_90
\inb[5]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \inb[5]~I_modesel\,
	dataout => \inb[5]~dataout\,
	padio => ww_inb(5));

-- atom is at PIN_51
\inb[4]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \inb[4]~I_modesel\,
	dataout => \inb[4]~dataout\,
	padio => ww_inb(4));

-- atom is at PIN_22
\inb[3]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \inb[3]~I_modesel\,
	dataout => \inb[3]~dataout\,
	padio => ww_inb(3));

-- atom is at PIN_55
\inb[2]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \inb[2]~I_modesel\,
	dataout => \inb[2]~dataout\,
	padio => ww_inb(2));

-- atom is at PIN_56
\inb[1]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \inb[1]~I_modesel\,
	dataout => \inb[1]~dataout\,
	padio => ww_inb(1));

-- atom is at PIN_124
\inb[0]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \inb[0]~I_modesel\,
	dataout => \inb[0]~dataout\,
	padio => ww_inb(0));

-- atom is at PIN_21
\cin~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \cin~I_modesel\,
	dataout => \cin~dataout\,
	padio => ww_cin);

-- atom is at LC4_D31
\Add0|adder|result_node|cs_buffer[0]~I\ : flex10ke_lcell
-- Equation(s):
-- \Add0|adder|result_node|cout[0]\ = CARRY(\cin~dataout\)

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "00CC",
--	operation_mode => "arithmetic",
--	output_mode => "none",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \Add0|adder|result_node|cs_buffer[0]~I_pathsel\,
	dataa => VCC,
	datab => \cin~dataout\,
	datac => VCC,
	datad => VCC,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \Add0|adder|result_node|cs_buffer[0]~I_modesel\,
	cout => \Add0|adder|result_node|cout[0]\);

-- atom is at LC5_D31
\Add0|adder|result_node|cs_buffer[1]~I\ : flex10ke_lcell
-- Equation(s):
-- \Add0|adder|result_node|cs_buffer[1]\ = \ina[0]~dataout\ $ \inb[0]~dataout\ $ \Add0|adder|result_node|cout[0]\
-- \Add0|adder|result_node|cout[1]\ = CARRY(\ina[0]~dataout\ & (\inb[0]~dataout\ # \Add0|adder|result_node|cout[0]\) # !\ina[0]~dataout\ & \inb[0]~dataout\ & \Add0|adder|result_node|cout[0]\)

-- pragma translate_off
-- GENERIC MAP (
--	cin_used => "true",
--	clock_enable_mode => "false",
--	lut_mask => "96E8",
--	operation_mode => "arithmetic",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \Add0|adder|result_node|cs_buffer[1]~I_pathsel\,
	dataa => \ina[0]~dataout\,
	datab => \inb[0]~dataout\,
	datac => VCC,
	datad => VCC,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => \Add0|adder|result_node|cout[0]\,
	cascin => VCC,
	modesel => \Add0|adder|result_node|cs_buffer[1]~I_modesel\,
	combout => \Add0|adder|result_node|cs_buffer[1]\,
	cout => \Add0|adder|result_node|cout[1]\);

-- atom is at LC6_D31
\Add0|adder|result_node|cs_buffer[2]~I\ : flex10ke_lcell
-- Equation(s):
-- \Add0|adder|result_node|cs_buffer[2]\ = \ina[1]~dataout\ $ \inb[1]~dataout\ $ \Add0|adder|result_node|cout[1]\
-- \Add0|adder|result_node|cout[2]\ = CARRY(\ina[1]~dataout\ & (\inb[1]~dataout\ # \Add0|adder|result_node|cout[1]\) # !\ina[1]~dataout\ & \inb[1]~dataout\ & \Add0|adder|result_node|cout[1]\)

-- pragma translate_off
-- GENERIC MAP (
--	cin_used => "true",
--	clock_enable_mode => "false",
--	lut_mask => "96E8",
--	operation_mode => "arithmetic",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \Add0|adder|result_node|cs_buffer[2]~I_pathsel\,
	dataa => \ina[1]~dataout\,
	datab => \inb[1]~dataout\,
	datac => VCC,
	datad => VCC,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => \Add0|adder|result_node|cout[1]\,
	cascin => VCC,
	modesel => \Add0|adder|result_node|cs_buffer[2]~I_modesel\,
	combout => \Add0|adder|result_node|cs_buffer[2]\,
	cout => \Add0|adder|result_node|cout[2]\);

-- atom is at LC7_D31
\Add0|adder|result_node|cs_buffer[3]~I\ : flex10ke_lcell
-- Equation(s):
-- \Add0|adder|result_node|cs_buffer[3]\ = \ina[2]~dataout\ $ \inb[2]~dataout\ $ \Add0|adder|result_node|cout[2]\
-- \Add0|adder|result_node|cout[3]\ = CARRY(\ina[2]~dataout\ & (\inb[2]~dataout\ # \Add0|adder|result_node|cout[2]\) # !\ina[2]~dataout\ & \inb[2]~dataout\ & \Add0|adder|result_node|cout[2]\)

-- pragma translate_off
-- GENERIC MAP (
--	cin_used => "true",