📄 _8bitfulladd.sim.rpt
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; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ; cout ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; data_out0 ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ; cout ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; data_out0 ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ; cout ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; data_out0 ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ; cout ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] ; data_out0 ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] ; cout ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] ; data_out0 ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] ; cout ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; cout ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~172 ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~172 ; data_out0 ;
; |_8bitFullAdd|ina[0] ; |_8bitFullAdd|ina[0] ; dataout ;
; |_8bitFullAdd|inb[0] ; |_8bitFullAdd|inb[0] ; dataout ;
; |_8bitFullAdd|ina[1] ; |_8bitFullAdd|ina[1] ; dataout ;
; |_8bitFullAdd|inb[1] ; |_8bitFullAdd|inb[1] ; dataout ;
; |_8bitFullAdd|ina[2] ; |_8bitFullAdd|ina[2] ; dataout ;
; |_8bitFullAdd|inb[2] ; |_8bitFullAdd|inb[2] ; dataout ;
; |_8bitFullAdd|ina[3] ; |_8bitFullAdd|ina[3] ; dataout ;
; |_8bitFullAdd|inb[3] ; |_8bitFullAdd|inb[3] ; dataout ;
; |_8bitFullAdd|ina[4] ; |_8bitFullAdd|ina[4] ; dataout ;
; |_8bitFullAdd|inb[4] ; |_8bitFullAdd|inb[4] ; dataout ;
; |_8bitFullAdd|ina[5] ; |_8bitFullAdd|ina[5] ; dataout ;
; |_8bitFullAdd|inb[5] ; |_8bitFullAdd|inb[5] ; dataout ;
; |_8bitFullAdd|ina[6] ; |_8bitFullAdd|ina[6] ; dataout ;
; |_8bitFullAdd|inb[6] ; |_8bitFullAdd|inb[6] ; dataout ;
; |_8bitFullAdd|ina[7] ; |_8bitFullAdd|ina[7] ; dataout ;
; |_8bitFullAdd|inb[7] ; |_8bitFullAdd|inb[7] ; dataout ;
; |_8bitFullAdd|cin ; |_8bitFullAdd|cin ; dataout ;
; |_8bitFullAdd|cout ; |_8bitFullAdd|cout ; padio ;
; |_8bitFullAdd|sum[0] ; |_8bitFullAdd|sum[0] ; padio ;
; |_8bitFullAdd|sum[1] ; |_8bitFullAdd|sum[1] ; padio ;
; |_8bitFullAdd|sum[2] ; |_8bitFullAdd|sum[2] ; padio ;
; |_8bitFullAdd|sum[3] ; |_8bitFullAdd|sum[3] ; padio ;
; |_8bitFullAdd|sum[4] ; |_8bitFullAdd|sum[4] ; padio ;
; |_8bitFullAdd|sum[5] ; |_8bitFullAdd|sum[5] ; padio ;
; |_8bitFullAdd|sum[6] ; |_8bitFullAdd|sum[6] ; padio ;
; |_8bitFullAdd|sum[7] ; |_8bitFullAdd|sum[7] ; padio ;
+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------------+
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; data_out0 ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[1] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[1] ; cout ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; data_out0 ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[2] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[2] ; cout ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; data_out0 ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[3] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[3] ; cout ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; data_out0 ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[4] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[4] ; cout ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; data_out0 ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[5] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[5] ; cout ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; data_out0 ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[6] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[6] ; cout ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] ; data_out0 ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[7] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[7] ; cout ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] ; data_out0 ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[8] ; cout ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cout[0] ; cout ;
; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~172 ; |_8bitFullAdd|lpm_add_sub:Add0|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]~172 ; data_out0 ;
; |_8bitFullAdd|ina[0] ; |_8bitFullAdd|ina[0] ; dataout ;
; |_8bitFullAdd|inb[0] ; |_8bitFullAdd|inb[0] ; dataout ;
; |_8bitFullAdd|ina[1] ; |_8bitFullAdd|ina[1] ; dataout ;
; |_8bitFullAdd|inb[1] ; |_8bitFullAdd|inb[1] ; dataout ;
; |_8bitFullAdd|ina[2] ; |_8bitFullAdd|ina[2] ; dataout ;
; |_8bitFullAdd|inb[2] ; |_8bitFullAdd|inb[2] ; dataout ;
; |_8bitFullAdd|ina[3] ; |_8bitFullAdd|ina[3] ; dataout ;
; |_8bitFullAdd|inb[3] ; |_8bitFullAdd|inb[3] ; dataout ;
; |_8bitFullAdd|ina[4] ; |_8bitFullAdd|ina[4] ; dataout ;
; |_8bitFullAdd|inb[4] ; |_8bitFullAdd|inb[4] ; dataout ;
; |_8bitFullAdd|ina[5] ; |_8bitFullAdd|ina[5] ; dataout ;
; |_8bitFullAdd|inb[5] ; |_8bitFullAdd|inb[5] ; dataout ;
; |_8bitFullAdd|ina[6] ; |_8bitFullAdd|ina[6] ; dataout ;
; |_8bitFullAdd|inb[6] ; |_8bitFullAdd|inb[6] ; dataout ;
; |_8bitFullAdd|ina[7] ; |_8bitFullAdd|ina[7] ; dataout ;
; |_8bitFullAdd|inb[7] ; |_8bitFullAdd|inb[7] ; dataout ;
; |_8bitFullAdd|cin ; |_8bitFullAdd|cin ; dataout ;
; |_8bitFullAdd|cout ; |_8bitFullAdd|cout ; padio ;
; |_8bitFullAdd|sum[0] ; |_8bitFullAdd|sum[0] ; padio ;
; |_8bitFullAdd|sum[1] ; |_8bitFullAdd|sum[1] ; padio ;
; |_8bitFullAdd|sum[2] ; |_8bitFullAdd|sum[2] ; padio ;
; |_8bitFullAdd|sum[3] ; |_8bitFullAdd|sum[3] ; padio ;
; |_8bitFullAdd|sum[4] ; |_8bitFullAdd|sum[4] ; padio ;
; |_8bitFullAdd|sum[5] ; |_8bitFullAdd|sum[5] ; padio ;
; |_8bitFullAdd|sum[6] ; |_8bitFullAdd|sum[6] ; padio ;
; |_8bitFullAdd|sum[7] ; |_8bitFullAdd|sum[7] ; padio ;
+---------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Sun May 18 10:19:46 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off _8bitFullAdd -c _8bitFullAdd
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 0.00 %
Info: Number of transitions in simulation is 0
Info: Vector file _8bitFullAdd.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Processing ended: Sun May 18 10:19:47 2008
Info: Elapsed time: 00:00:01
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