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📄 _8bitfulladd.vo

📁 有用的verilog hdl实验用程序 配有截图
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// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

// DATE "05/18/2008 10:16:24"

// 
// Device: Altera EP1K30TC144-3 Package TQFP144
// 

// 
// This Verilog file should be used for Active-HDL (Verilog) only
// 

`timescale 1 ps/ 1 ps

module _8bitFullAdd (
	cout,
	sum,
	ina,
	inb,
	cin);
output 	cout;
output 	[7:0] sum;
input 	[7:0] ina;
input 	[7:0] inb;
input 	cin;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("_8bitFullAdd_v.sdo");
// synopsys translate_on

wire \cin~dataout ;
wire \Add0|adder|result_node|cs_buffer[8]~172 ;
wire [7:0] \ina~dataout ;
wire [7:0] \inb~dataout ;
wire [9:0] \Add0|adder|result_node|cout ;
wire [9:0] \Add0|adder|result_node|cs_buffer ;


// atom is at PIN_132
flex10ke_io \inb[7]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\inb~dataout [7]),
	.padio(inb[7]));
// synopsys translate_off
defparam \inb[7]~I .feedback_mode = "from_pin";
defparam \inb[7]~I .operation_mode = "input";
defparam \inb[7]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_143
flex10ke_io \inb[6]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\inb~dataout [6]),
	.padio(inb[6]));
// synopsys translate_off
defparam \inb[6]~I .feedback_mode = "from_pin";
defparam \inb[6]~I .operation_mode = "input";
defparam \inb[6]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_90
flex10ke_io \inb[5]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\inb~dataout [5]),
	.padio(inb[5]));
// synopsys translate_off
defparam \inb[5]~I .feedback_mode = "from_pin";
defparam \inb[5]~I .operation_mode = "input";
defparam \inb[5]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_51
flex10ke_io \inb[4]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\inb~dataout [4]),
	.padio(inb[4]));
// synopsys translate_off
defparam \inb[4]~I .feedback_mode = "from_pin";
defparam \inb[4]~I .operation_mode = "input";
defparam \inb[4]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_22
flex10ke_io \inb[3]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\inb~dataout [3]),
	.padio(inb[3]));
// synopsys translate_off
defparam \inb[3]~I .feedback_mode = "from_pin";
defparam \inb[3]~I .operation_mode = "input";
defparam \inb[3]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_55
flex10ke_io \inb[2]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\inb~dataout [2]),
	.padio(inb[2]));
// synopsys translate_off
defparam \inb[2]~I .feedback_mode = "from_pin";
defparam \inb[2]~I .operation_mode = "input";
defparam \inb[2]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_56
flex10ke_io \inb[1]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\inb~dataout [1]),
	.padio(inb[1]));
// synopsys translate_off
defparam \inb[1]~I .feedback_mode = "from_pin";
defparam \inb[1]~I .operation_mode = "input";
defparam \inb[1]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_124
flex10ke_io \inb[0]~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\inb~dataout [0]),
	.padio(inb[0]));
// synopsys translate_off
defparam \inb[0]~I .feedback_mode = "from_pin";
defparam \inb[0]~I .operation_mode = "input";
defparam \inb[0]~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at PIN_21
flex10ke_io \cin~I (
	.datain(gnd),
	.clk(gnd),
	.ena(vcc),
	.aclr(gnd),
	.oe(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.dataout(\cin~dataout ),
	.padio(cin));
// synopsys translate_off
defparam \cin~I .feedback_mode = "from_pin";
defparam \cin~I .operation_mode = "input";
defparam \cin~I .reg_source_mode = "none";
// synopsys translate_on

// atom is at LC4_D31
flex10ke_lcell \Add0|adder|result_node|cs_buffer[0]~I (
// Equation(s):
// \Add0|adder|result_node|cout [0] = CARRY(\cin~dataout )

	.dataa(vcc),
	.datab(\cin~dataout ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(gnd),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Add0|adder|result_node|cs_buffer [0]),
	.regout(),
	.cout(\Add0|adder|result_node|cout [0]),
	.cascout());
// synopsys translate_off
defparam \Add0|adder|result_node|cs_buffer[0]~I .clock_enable_mode = "false";
defparam \Add0|adder|result_node|cs_buffer[0]~I .lut_mask = "00CC";
defparam \Add0|adder|result_node|cs_buffer[0]~I .operation_mode = "arithmetic";
defparam \Add0|adder|result_node|cs_buffer[0]~I .output_mode = "none";
defparam \Add0|adder|result_node|cs_buffer[0]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC5_D31
flex10ke_lcell \Add0|adder|result_node|cs_buffer[1]~I (
// Equation(s):
// \Add0|adder|result_node|cs_buffer [1] = \ina~dataout [0] $ \inb~dataout [0] $ \Add0|adder|result_node|cout [0]
// \Add0|adder|result_node|cout [1] = CARRY(\ina~dataout [0] & (\inb~dataout [0] # \Add0|adder|result_node|cout [0]) # !\ina~dataout [0] & \inb~dataout [0] & \Add0|adder|result_node|cout [0])

	.dataa(\ina~dataout [0]),
	.datab(\inb~dataout [0]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Add0|adder|result_node|cout [0]),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Add0|adder|result_node|cs_buffer [1]),
	.regout(),
	.cout(\Add0|adder|result_node|cout [1]),
	.cascout());
// synopsys translate_off
defparam \Add0|adder|result_node|cs_buffer[1]~I .cin_used = "true";
defparam \Add0|adder|result_node|cs_buffer[1]~I .clock_enable_mode = "false";
defparam \Add0|adder|result_node|cs_buffer[1]~I .lut_mask = "96E8";
defparam \Add0|adder|result_node|cs_buffer[1]~I .operation_mode = "arithmetic";
defparam \Add0|adder|result_node|cs_buffer[1]~I .output_mode = "comb_only";
defparam \Add0|adder|result_node|cs_buffer[1]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC6_D31
flex10ke_lcell \Add0|adder|result_node|cs_buffer[2]~I (
// Equation(s):
// \Add0|adder|result_node|cs_buffer [2] = \ina~dataout [1] $ \inb~dataout [1] $ \Add0|adder|result_node|cout [1]
// \Add0|adder|result_node|cout [2] = CARRY(\ina~dataout [1] & (\inb~dataout [1] # \Add0|adder|result_node|cout [1]) # !\ina~dataout [1] & \inb~dataout [1] & \Add0|adder|result_node|cout [1])

	.dataa(\ina~dataout [1]),
	.datab(\inb~dataout [1]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Add0|adder|result_node|cout [1]),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Add0|adder|result_node|cs_buffer [2]),
	.regout(),
	.cout(\Add0|adder|result_node|cout [2]),
	.cascout());
// synopsys translate_off
defparam \Add0|adder|result_node|cs_buffer[2]~I .cin_used = "true";
defparam \Add0|adder|result_node|cs_buffer[2]~I .clock_enable_mode = "false";
defparam \Add0|adder|result_node|cs_buffer[2]~I .lut_mask = "96E8";
defparam \Add0|adder|result_node|cs_buffer[2]~I .operation_mode = "arithmetic";
defparam \Add0|adder|result_node|cs_buffer[2]~I .output_mode = "comb_only";
defparam \Add0|adder|result_node|cs_buffer[2]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC7_D31
flex10ke_lcell \Add0|adder|result_node|cs_buffer[3]~I (
// Equation(s):
// \Add0|adder|result_node|cs_buffer [3] = \ina~dataout [2] $ \inb~dataout [2] $ \Add0|adder|result_node|cout [2]
// \Add0|adder|result_node|cout [3] = CARRY(\ina~dataout [2] & (\inb~dataout [2] # \Add0|adder|result_node|cout [2]) # !\ina~dataout [2] & \inb~dataout [2] & \Add0|adder|result_node|cout [2])

	.dataa(\ina~dataout [2]),
	.datab(\inb~dataout [2]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Add0|adder|result_node|cout [2]),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Add0|adder|result_node|cs_buffer [3]),
	.regout(),
	.cout(\Add0|adder|result_node|cout [3]),
	.cascout());
// synopsys translate_off
defparam \Add0|adder|result_node|cs_buffer[3]~I .cin_used = "true";
defparam \Add0|adder|result_node|cs_buffer[3]~I .clock_enable_mode = "false";
defparam \Add0|adder|result_node|cs_buffer[3]~I .lut_mask = "96E8";
defparam \Add0|adder|result_node|cs_buffer[3]~I .operation_mode = "arithmetic";
defparam \Add0|adder|result_node|cs_buffer[3]~I .output_mode = "comb_only";
defparam \Add0|adder|result_node|cs_buffer[3]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC8_D31
flex10ke_lcell \Add0|adder|result_node|cs_buffer[4]~I (
// Equation(s):
// \Add0|adder|result_node|cs_buffer [4] = \ina~dataout [3] $ \inb~dataout [3] $ \Add0|adder|result_node|cout [3]
// \Add0|adder|result_node|cout [4] = CARRY(\ina~dataout [3] & (\inb~dataout [3] # \Add0|adder|result_node|cout [3]) # !\ina~dataout [3] & \inb~dataout [3] & \Add0|adder|result_node|cout [3])

	.dataa(\ina~dataout [3]),
	.datab(\inb~dataout [3]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Add0|adder|result_node|cout [3]),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Add0|adder|result_node|cs_buffer [4]),
	.regout(),
	.cout(\Add0|adder|result_node|cout [4]),
	.cascout());
// synopsys translate_off
defparam \Add0|adder|result_node|cs_buffer[4]~I .cin_used = "true";
defparam \Add0|adder|result_node|cs_buffer[4]~I .clock_enable_mode = "false";
defparam \Add0|adder|result_node|cs_buffer[4]~I .lut_mask = "96E8";
defparam \Add0|adder|result_node|cs_buffer[4]~I .operation_mode = "arithmetic";
defparam \Add0|adder|result_node|cs_buffer[4]~I .output_mode = "comb_only";
defparam \Add0|adder|result_node|cs_buffer[4]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC1_D33
flex10ke_lcell \Add0|adder|result_node|cs_buffer[5]~I (
// Equation(s):
// \Add0|adder|result_node|cs_buffer [5] = \ina~dataout [4] $ \inb~dataout [4] $ \Add0|adder|result_node|cout [4]
// \Add0|adder|result_node|cout [5] = CARRY(\ina~dataout [4] & (\inb~dataout [4] # \Add0|adder|result_node|cout [4]) # !\ina~dataout [4] & \inb~dataout [4] & \Add0|adder|result_node|cout [4])

	.dataa(\ina~dataout [4]),
	.datab(\inb~dataout [4]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Add0|adder|result_node|cout [4]),
	.cascin(vcc),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Add0|adder|result_node|cs_buffer [5]),
	.regout(),
	.cout(\Add0|adder|result_node|cout [5]),
	.cascout());
// synopsys translate_off
defparam \Add0|adder|result_node|cs_buffer[5]~I .cin_used = "true";
defparam \Add0|adder|result_node|cs_buffer[5]~I .clock_enable_mode = "false";
defparam \Add0|adder|result_node|cs_buffer[5]~I .lut_mask = "96E8";
defparam \Add0|adder|result_node|cs_buffer[5]~I .operation_mode = "arithmetic";
defparam \Add0|adder|result_node|cs_buffer[5]~I .output_mode = "comb_only";
defparam \Add0|adder|result_node|cs_buffer[5]~I .packed_mode = "false";
// synopsys translate_on

// atom is at LC2_D33
flex10ke_lcell \Add0|adder|result_node|cs_buffer[6]~I (
// Equation(s):
// \Add0|adder|result_node|cs_buffer [6] = \ina~dataout [5] $ \inb~dataout [5] $ \Add0|adder|result_node|cout [5]
// \Add0|adder|result_node|cout [6] = CARRY(\ina~dataout [5] & (\inb~dataout [5] # \Add0|adder|result_node|cout [5]) # !\ina~dataout [5] & \inb~dataout [5] & \Add0|adder|result_node|cout [5])

	.dataa(\ina~dataout [5]),
	.datab(\inb~dataout [5]),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.clk(gnd),
	.cin(\Add0|adder|result_node|cout [5]),
12

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