testlist.tan.qmsg

有用的verilog hdl实验用程序 配有截图

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 18 10:09:09 2008 " "Info: Processing started: Sun May 18 10:09:09 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off testlist -c testlist " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off testlist -c testlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "list\[1\] result\[8\] 24.200 ns Longest " "Info: Longest tpd from source pin \"list\[1\]\" to destination pin \"result\[8\]\" is 24.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns list\[1\] 1 PIN PIN_8 5 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_8; Fanout = 5; PIN Node = 'list\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { list[1] } "NODE_NAME" } } { "testlist.v" "" { Text "F:/testlist/testlist.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.300 ns) + CELL(1.700 ns) 9.900 ns WideOr1~187 2 COMB LC1_C27 1 " "Info: 2: + IC(3.300 ns) + CELL(1.700 ns) = 9.900 ns; Loc. = LC1_C27; Fanout = 1; COMB Node = 'WideOr1~187'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.000 ns" { list[1] WideOr1~187 } "NODE_NAME" } } { "testlist.v" "" { Text "F:/testlist/testlist.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.600 ns) 12.800 ns WideOr1~188 3 COMB LC1_C21 5 " "Info: 3: + IC(1.300 ns) + CELL(1.600 ns) = 12.800 ns; Loc. = LC1_C21; Fanout = 5; COMB Node = 'WideOr1~188'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.900 ns" { WideOr1~187 WideOr1~188 } "NODE_NAME" } } { "testlist.v" "" { Text "F:/testlist/testlist.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.600 ns) 15.800 ns WideOr0~144 4 COMB LC7_C29 1 " "Info: 4: + IC(1.400 ns) + CELL(1.600 ns) = 15.800 ns; Loc. = LC7_C29; Fanout = 1; COMB Node = 'WideOr0~144'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { WideOr1~188 WideOr0~144 } "NODE_NAME" } } { "testlist.v" "" { Text "F:/testlist/testlist.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(6.300 ns) 24.200 ns result\[8\] 5 PIN PIN_29 0 " "Info: 5: + IC(2.100 ns) + CELL(6.300 ns) = 24.200 ns; Loc. = PIN_29; Fanout = 0; PIN Node = 'result\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.400 ns" { WideOr0~144 result[8] } "NODE_NAME" } } { "testlist.v" "" { Text "F:/testlist/testlist.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "16.100 ns ( 66.53 % ) " "Info: Total cell delay = 16.100 ns ( 66.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.100 ns ( 33.47 % ) " "Info: Total interconnect delay = 8.100 ns ( 33.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "24.200 ns" { list[1] WideOr1~187 WideOr1~188 WideOr0~144 result[8] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "24.200 ns" { list[1] list[1]~out WideOr1~187 WideOr1~188 WideOr0~144 result[8] } { 0.000ns 0.000ns 3.300ns 1.300ns 1.400ns 2.100ns } { 0.000ns 4.900ns 1.700ns 1.600ns 1.600ns 6.300ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 18 10:09:09 2008 " "Info: Processing ended: Sun May 18 10:09:09 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}