testlist.vho

有用的verilog hdl实验用程序 配有截图

	combout => \WideOr3~49\);

-- atom is at PIN_19
\list[8]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \list[8]~I_modesel\,
	dataout => \list[8]~dataout\,
	padio => ww_list(8));

-- atom is at LC3_C27
\WideOr3~50_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr3~50\ = \list[1]~dataout\ & !\list[5]~dataout\ & !\list[8]~dataout\ & !\list[4]~dataout\ # !\list[1]~dataout\ & (\list[5]~dataout\ & !\list[8]~dataout\ & !\list[4]~dataout\ # !\list[5]~dataout\ & (\list[8]~dataout\ $ \list[4]~dataout\))

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "0116",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr3~50_I_pathsel\,
	dataa => \list[1]~dataout\,
	datab => \list[5]~dataout\,
	datac => \list[8]~dataout\,
	datad => \list[4]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr3~50_I_modesel\,
	combout => \WideOr3~50\);

-- atom is at LC4_C21
\WideOr3~51_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr3~51\ = \WideOr3~49\ & \WideOr3~50\ & !\list[7]~dataout\ & !\list[6]~dataout\

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "0008",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr3~51_I_pathsel\,
	dataa => \WideOr3~49\,
	datab => \WideOr3~50\,
	datac => \list[7]~dataout\,
	datad => \list[6]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr3~51_I_modesel\,
	combout => \WideOr3~51\);

-- atom is at LC8_C27
\WideOr2~49_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr2~49\ = \list[1]~dataout\ & !\list[2]~dataout\ & !\list[3]~dataout\ & !\list[8]~dataout\ # !\list[1]~dataout\ & (\list[2]~dataout\ & !\list[3]~dataout\ & !\list[8]~dataout\ # !\list[2]~dataout\ & (\list[3]~dataout\ $ \list[8]~dataout\))

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "0116",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr2~49_I_pathsel\,
	dataa => \list[1]~dataout\,
	datab => \list[2]~dataout\,
	datac => \list[3]~dataout\,
	datad => \list[8]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr2~49_I_modesel\,
	combout => \WideOr2~49\);

-- atom is at LC6_C27
\WideOr2~50_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr2~50\ = \WideOr2~48\ & \WideOr2~49\ & !\list[6]~dataout\ & !\list[4]~dataout\

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "0008",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr2~50_I_pathsel\,
	dataa => \WideOr2~48\,
	datab => \WideOr2~49\,
	datac => \list[6]~dataout\,
	datad => \list[4]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr2~50_I_modesel\,
	combout => \WideOr2~50\);

-- atom is at LC6_C21
\WideOr1~186_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr1~186\ = !\list[4]~dataout\ & !\list[1]~dataout\ & !\list[2]~dataout\ & !\list[3]~dataout\

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "0001",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr1~186_I_pathsel\,
	dataa => \list[4]~dataout\,
	datab => \list[1]~dataout\,
	datac => \list[2]~dataout\,
	datad => \list[3]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr1~186_I_modesel\,
	combout => \WideOr1~186\);

-- atom is at LC2_C21
\WideOr0~138_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr0~138\ = \WideOr1~186\ & !\list[5]~dataout\ & !\list[6]~dataout\

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "000C",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr0~138_I_pathsel\,
	dataa => VCC,
	datab => \WideOr1~186\,
	datac => \list[5]~dataout\,
	datad => \list[6]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr0~138_I_modesel\,
	combout => \WideOr0~138\);

-- atom is at LC1_C27
\WideOr1~187_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr1~187\ = \list[1]~dataout\ & !\list[2]~dataout\ & !\list[3]~dataout\ & !\list[4]~dataout\ # !\list[1]~dataout\ & (\list[2]~dataout\ & !\list[3]~dataout\ & !\list[4]~dataout\ # !\list[2]~dataout\ & (\list[3]~dataout\ $ \list[4]~dataout\))

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "0116",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr1~187_I_pathsel\,
	dataa => \list[1]~dataout\,
	datab => \list[2]~dataout\,
	datac => \list[3]~dataout\,
	datad => \list[4]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr1~187_I_modesel\,
	combout => \WideOr1~187\);

-- atom is at LC1_C21
\WideOr1~188_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr1~188\ = \list[5]~dataout\ & \WideOr1~186\ & (!\list[6]~dataout\) # !\list[5]~dataout\ & (\list[6]~dataout\ & \WideOr1~186\ # !\list[6]~dataout\ & (\WideOr1~187\))

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "0AAC",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr1~188_I_pathsel\,
	dataa => \WideOr1~186\,
	datab => \WideOr1~187\,
	datac => \list[5]~dataout\,
	datad => \list[6]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr1~188_I_modesel\,
	combout => \WideOr1~188\);

-- atom is at LC7_C27
\WideOr1~189_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr1~189\ = !\list[8]~dataout\ & (\list[7]~dataout\ & \WideOr0~138\ # !\list[7]~dataout\ & (\WideOr1~188\))

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "00AC",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr1~189_I_pathsel\,
	dataa => \WideOr0~138\,
	datab => \WideOr1~188\,
	datac => \list[7]~dataout\,
	datad => \list[8]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr1~189_I_modesel\,
	combout => \WideOr1~189\);

-- atom is at LC1_C34
\WideOr0~139_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr0~139\ = \list[8]~dataout\ & \WideOr0~138\ & (!\list[7]~dataout\) # !\list[8]~dataout\ & (\list[7]~dataout\ & \WideOr0~138\ # !\list[7]~dataout\ & (\WideOr1~188\))

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "0AAC",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr0~139_I_pathsel\,
	dataa => \WideOr0~138\,
	datab => \WideOr1~188\,
	datac => \list[8]~dataout\,
	datad => \list[7]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr0~139_I_modesel\,
	combout => \WideOr0~139\);

-- atom is at LC3_C21
\WideOr0~142_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr0~142\ = \list[8]~dataout\ & \WideOr0~138\ & (!\list[7]~dataout\) # !\list[8]~dataout\ & (\list[7]~dataout\ & \WideOr0~138\ # !\list[7]~dataout\ & (\WideOr1~188\))

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "0AAC",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr0~142_I_pathsel\,
	dataa => \WideOr0~138\,
	datab => \WideOr1~188\,
	datac => \list[8]~dataout\,
	datad => \list[7]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr0~142_I_modesel\,
	combout => \WideOr0~142\);

-- atom is at LC5_C26
\WideOr0~143_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr0~143\ = \list[8]~dataout\ & \WideOr0~138\ & (!\list[7]~dataout\) # !\list[8]~dataout\ & (\list[7]~dataout\ & \WideOr0~138\ # !\list[7]~dataout\ & (\WideOr1~188\))

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "0AAC",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr0~143_I_pathsel\,
	dataa => \WideOr0~138\,
	datab => \WideOr1~188\,
	datac => \list[8]~dataout\,
	datad => \list[7]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr0~143_I_modesel\,
	combout => \WideOr0~143\);

-- atom is at LC7_C29
\WideOr0~144_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr0~144\ = \list[8]~dataout\ & \WideOr0~138\ & (!\list[7]~dataout\) # !\list[8]~dataout\ & (\list[7]~dataout\ & \WideOr0~138\ # !\list[7]~dataout\ & (\WideOr1~188\))

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "0AAC",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr0~144_I_pathsel\,
	dataa => \WideOr0~138\,
	datab => \WideOr1~188\,
	datac => \list[8]~dataout\,
	datad => \list[7]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr0~144_I_modesel\,
	combout => \WideOr0~144\);

-- atom is at PIN_20
\result[1]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_WideOr4~48\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \result[1]~I_modesel\,
	padio => ww_result(1));

-- atom is at PIN_21
\result[2]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_WideOr3~51\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \result[2]~I_modesel\,
	padio => ww_result(2));

-- atom is at PIN_22
\result[3]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_WideOr2~50\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \result[3]~I_modesel\,
	padio => ww_result(3));

-- atom is at PIN_23
\result[4]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_WideOr1~189\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \result[4]~I_modesel\,
	padio => ww_result(4));

-- atom is at PIN_26
\result[5]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_WideOr0~139\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \result[5]~I_modesel\,
	padio => ww_result(5));

-- atom is at PIN_27
\result[6]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_WideOr0~142\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \result[6]~I_modesel\,
	padio => ww_result(6));

-- atom is at PIN_28
\result[7]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_WideOr0~143\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \result[7]~I_modesel\,
	padio => ww_result(7));

-- atom is at PIN_29
\result[8]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "none",
--	operation_mode => "output",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => \ALT_INV_WideOr0~144\,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => VCC,
	modesel => \result[8]~I_modesel\,
	padio => ww_result(8));
END structure;