testlist.vho

有用的verilog hdl实验用程序 配有截图

-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

-- DATE "05/18/2008 10:09:12"

-- 
-- Device: Altera EP1K30TC144-3 Package TQFP144
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	testlist IS
    PORT (
	list : IN std_logic_vector(8 DOWNTO 1);
	result : OUT std_logic_vector(8 DOWNTO 1)
	);
END testlist;

ARCHITECTURE structure OF testlist IS
SIGNAL GNDs : std_logic_vector(1024 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(1024 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_list : std_logic_vector(8 DOWNTO 1);
SIGNAL ww_result : std_logic_vector(8 DOWNTO 1);
SIGNAL \list[7]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \list[5]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \WideOr2~48_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr2~48_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \list[2]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \list[6]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \list[4]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \WideOr4~47_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr4~47_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \list[1]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \list[3]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \WideOr4~48_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr4~48_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \WideOr3~49_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr3~49_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \list[8]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \WideOr3~50_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr3~50_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \WideOr3~51_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr3~51_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \WideOr2~49_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr2~49_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \WideOr2~50_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr2~50_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \WideOr1~186_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr1~186_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \WideOr0~138_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr0~138_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \WideOr1~187_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr1~187_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \WideOr1~188_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr1~188_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \WideOr1~189_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr1~189_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \WideOr0~139_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr0~139_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \WideOr0~142_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr0~142_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \WideOr0~143_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr0~143_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \WideOr0~144_I_modesel\ : std_logic_vector(6 DOWNTO 0);
SIGNAL \WideOr0~144_I_pathsel\ : std_logic_vector(9 DOWNTO 0);
SIGNAL \result[1]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \result[2]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \result[3]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \result[4]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \result[5]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \result[6]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \result[7]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \result[8]~I_modesel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \list[7]~dataout\ : std_logic;
SIGNAL \list[5]~dataout\ : std_logic;
SIGNAL \WideOr2~48\ : std_logic;
SIGNAL \list[2]~dataout\ : std_logic;
SIGNAL \list[6]~dataout\ : std_logic;
SIGNAL \list[4]~dataout\ : std_logic;
SIGNAL \WideOr4~47\ : std_logic;
SIGNAL \list[1]~dataout\ : std_logic;
SIGNAL \list[3]~dataout\ : std_logic;
SIGNAL \WideOr4~48\ : std_logic;
SIGNAL \WideOr3~49\ : std_logic;
SIGNAL \list[8]~dataout\ : std_logic;
SIGNAL \WideOr3~50\ : std_logic;
SIGNAL \WideOr3~51\ : std_logic;
SIGNAL \WideOr2~49\ : std_logic;
SIGNAL \WideOr2~50\ : std_logic;
SIGNAL \WideOr1~186\ : std_logic;
SIGNAL \WideOr0~138\ : std_logic;
SIGNAL \WideOr1~187\ : std_logic;
SIGNAL \WideOr1~188\ : std_logic;
SIGNAL \WideOr1~189\ : std_logic;
SIGNAL \WideOr0~139\ : std_logic;
SIGNAL \WideOr0~142\ : std_logic;
SIGNAL \WideOr0~143\ : std_logic;
SIGNAL \WideOr0~144\ : std_logic;
SIGNAL \ALT_INV_WideOr4~48\ : std_logic;
SIGNAL \ALT_INV_WideOr3~51\ : std_logic;
SIGNAL \ALT_INV_WideOr2~50\ : std_logic;
SIGNAL \ALT_INV_WideOr1~189\ : std_logic;
SIGNAL \ALT_INV_WideOr0~139\ : std_logic;
SIGNAL \ALT_INV_WideOr0~142\ : std_logic;
SIGNAL \ALT_INV_WideOr0~143\ : std_logic;
SIGNAL \ALT_INV_WideOr0~144\ : std_logic;
COMPONENT flex10ke_lcell
PORT (
	dataa : IN STD_LOGIC;
	datab : IN STD_LOGIC;
	datac : IN STD_LOGIC;
	datad : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	aload : IN STD_LOGIC;
	clk : IN STD_LOGIC;
	cin : IN STD_LOGIC;
	cascin : IN STD_LOGIC;
	combout : OUT STD_LOGIC;
	regout : OUT STD_LOGIC;
	cout : OUT STD_LOGIC;
	cascout : OUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
	pathsel : IN STD_LOGIC_VECTOR(9 DOWNTO 0));
END COMPONENT;

COMPONENT flex10ke_io
PORT (
	datain : IN STD_LOGIC;
	clk : IN STD_LOGIC;
	ena : IN STD_LOGIC;
	aclr : IN STD_LOGIC;
	oe : IN STD_LOGIC;
	dataout : OUT STD_LOGIC;
	padio : INOUT STD_LOGIC;
	modesel : IN STD_LOGIC_VECTOR(10 DOWNTO 0));
END COMPONENT;


COMPONENT INV
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;

COMPONENT AND1
    PORT (
	IN1 : IN std_logic;
	Y :  OUT std_logic);
END COMPONENT;
BEGIN

ww_list <= list;
result <= ww_result;

gnd <= '0';
vcc <= '1';
GNDs <= (OTHERS => '0');
VCCs <= (OTHERS => '1');

\list[7]~I_modesel\ <= "01010000001";
\list[5]~I_modesel\ <= "01010000001";
\WideOr2~48_I_modesel\ <= "1000001";
\WideOr2~48_I_pathsel\ <= "0000001100";
\list[2]~I_modesel\ <= "01010000001";
\list[6]~I_modesel\ <= "01010000001";
\list[4]~I_modesel\ <= "01010000001";
\WideOr4~47_I_modesel\ <= "1000001";
\WideOr4~47_I_pathsel\ <= "0000001111";
\list[1]~I_modesel\ <= "01010000001";
\list[3]~I_modesel\ <= "01010000001";
\WideOr4~48_I_modesel\ <= "1000001";
\WideOr4~48_I_pathsel\ <= "0000001111";
\WideOr3~49_I_modesel\ <= "1000001";
\WideOr3~49_I_pathsel\ <= "0000001100";
\list[8]~I_modesel\ <= "01010000001";
\WideOr3~50_I_modesel\ <= "1000001";
\WideOr3~50_I_pathsel\ <= "0000001111";
\WideOr3~51_I_modesel\ <= "1000001";
\WideOr3~51_I_pathsel\ <= "0000001111";
\WideOr2~49_I_modesel\ <= "1000001";
\WideOr2~49_I_pathsel\ <= "0000001111";
\WideOr2~50_I_modesel\ <= "1000001";
\WideOr2~50_I_pathsel\ <= "0000001111";
\WideOr1~186_I_modesel\ <= "1000001";
\WideOr1~186_I_pathsel\ <= "0000001111";
\WideOr0~138_I_modesel\ <= "1000001";
\WideOr0~138_I_pathsel\ <= "0000001110";
\WideOr1~187_I_modesel\ <= "1000001";
\WideOr1~187_I_pathsel\ <= "0000001111";
\WideOr1~188_I_modesel\ <= "1000001";
\WideOr1~188_I_pathsel\ <= "0000001111";
\WideOr1~189_I_modesel\ <= "1000001";
\WideOr1~189_I_pathsel\ <= "0000001111";
\WideOr0~139_I_modesel\ <= "1000001";
\WideOr0~139_I_pathsel\ <= "0000001111";
\WideOr0~142_I_modesel\ <= "1000001";
\WideOr0~142_I_pathsel\ <= "0000001111";
\WideOr0~143_I_modesel\ <= "1000001";
\WideOr0~143_I_pathsel\ <= "0000001111";
\WideOr0~144_I_modesel\ <= "1000001";
\WideOr0~144_I_pathsel\ <= "0000001111";
\result[1]~I_modesel\ <= "10010000010";
\result[2]~I_modesel\ <= "10010000010";
\result[3]~I_modesel\ <= "10010000010";
\result[4]~I_modesel\ <= "10010000010";
\result[5]~I_modesel\ <= "10010000010";
\result[6]~I_modesel\ <= "10010000010";
\result[7]~I_modesel\ <= "10010000010";
\result[8]~I_modesel\ <= "10010000010";

\INV_INST_WideOr4~48\ : INV
PORT MAP (
	 IN1 => \WideOr4~48\,
	 Y => \ALT_INV_WideOr4~48\);

\INV_INST_WideOr3~51\ : INV
PORT MAP (
	 IN1 => \WideOr3~51\,
	 Y => \ALT_INV_WideOr3~51\);

\INV_INST_WideOr2~50\ : INV
PORT MAP (
	 IN1 => \WideOr2~50\,
	 Y => \ALT_INV_WideOr2~50\);

\INV_INST_WideOr1~189\ : INV
PORT MAP (
	 IN1 => \WideOr1~189\,
	 Y => \ALT_INV_WideOr1~189\);

\INV_INST_WideOr0~139\ : INV
PORT MAP (
	 IN1 => \WideOr0~139\,
	 Y => \ALT_INV_WideOr0~139\);

\INV_INST_WideOr0~142\ : INV
PORT MAP (
	 IN1 => \WideOr0~142\,
	 Y => \ALT_INV_WideOr0~142\);

\INV_INST_WideOr0~143\ : INV
PORT MAP (
	 IN1 => \WideOr0~143\,
	 Y => \ALT_INV_WideOr0~143\);

\INV_INST_WideOr0~144\ : INV
PORT MAP (
	 IN1 => \WideOr0~144\,
	 Y => \ALT_INV_WideOr0~144\);

lcell_ff_enable_asynch_arcs : AND1
PORT MAP (
	 IN1 => GND,
	 Y => lcell_ff_enable_asynch_arcs_out);

-- atom is at PIN_18
\list[7]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \list[7]~I_modesel\,
	dataout => \list[7]~dataout\,
	padio => ww_list(7));

-- atom is at PIN_13
\list[5]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \list[5]~I_modesel\,
	dataout => \list[5]~dataout\,
	padio => ww_list(5));

-- atom is at LC5_C21
\WideOr2~48_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr2~48\ = !\list[7]~dataout\ & !\list[5]~dataout\

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "000F",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr2~48_I_pathsel\,
	dataa => VCC,
	datab => VCC,
	datac => \list[7]~dataout\,
	datad => \list[5]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr2~48_I_modesel\,
	combout => \WideOr2~48\);

-- atom is at PIN_9
\list[2]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \list[2]~I_modesel\,
	dataout => \list[2]~dataout\,
	padio => ww_list(2));

-- atom is at PIN_17
\list[6]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \list[6]~I_modesel\,
	dataout => \list[6]~dataout\,
	padio => ww_list(6));

-- atom is at PIN_12
\list[4]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \list[4]~I_modesel\,
	dataout => \list[4]~dataout\,
	padio => ww_list(4));

-- atom is at LC5_C27
\WideOr4~47_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr4~47\ = \list[8]~dataout\ & !\list[2]~dataout\ & !\list[6]~dataout\ & !\list[4]~dataout\ # !\list[8]~dataout\ & (\list[2]~dataout\ & !\list[6]~dataout\ & !\list[4]~dataout\ # !\list[2]~dataout\ & (\list[6]~dataout\ $ \list[4]~dataout\))

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "0116",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr4~47_I_pathsel\,
	dataa => \list[8]~dataout\,
	datab => \list[2]~dataout\,
	datac => \list[6]~dataout\,
	datad => \list[4]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr4~47_I_modesel\,
	combout => \WideOr4~47\);

-- atom is at PIN_8
\list[1]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \list[1]~I_modesel\,
	dataout => \list[1]~dataout\,
	padio => ww_list(1));

-- atom is at PIN_10
\list[3]~I\ : flex10ke_io
-- pragma translate_off
-- GENERIC MAP (
--	feedback_mode => "from_pin",
--	operation_mode => "input",
--	reg_source_mode => "none")
-- pragma translate_on
PORT MAP (
	datain => GND,
	clk => GND,
	ena => VCC,
	aclr => GND,
	oe => GND,
	modesel => \list[3]~I_modesel\,
	dataout => \list[3]~dataout\,
	padio => ww_list(3));

-- atom is at LC2_C27
\WideOr4~48_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr4~48\ = \WideOr2~48\ & \WideOr4~47\ & !\list[1]~dataout\ & !\list[3]~dataout\

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "0008",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr4~48_I_pathsel\,
	dataa => \WideOr2~48\,
	datab => \WideOr4~47\,
	datac => \list[1]~dataout\,
	datad => \list[3]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr4~48_I_modesel\,
	combout => \WideOr4~48\);

-- atom is at LC4_C27
\WideOr3~49_I\ : flex10ke_lcell
-- Equation(s):
-- \WideOr3~49\ = !\list[2]~dataout\ & !\list[3]~dataout\

-- pragma translate_off
-- GENERIC MAP (
--	clock_enable_mode => "false",
--	lut_mask => "000F",
--	operation_mode => "normal",
--	output_mode => "comb_only",
--	packed_mode => "false")
-- pragma translate_on
PORT MAP (
	pathsel => \WideOr3~49_I_pathsel\,
	dataa => VCC,
	datab => VCC,
	datac => \list[2]~dataout\,
	datad => \list[3]~dataout\,
	aclr => GND,
	aload => GND,
	clk => GND,
	cin => GND,
	cascin => VCC,
	modesel => \WideOr3~49_I_modesel\,