testlist.qsf

有用的verilog hdl实验用程序 配有截图

# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		testlist_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY ACEX1K
set_global_assignment -name DEVICE "EP1K30TC144-3"
set_global_assignment -name TOP_LEVEL_ENTITY testlist
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:51:40  MAY 18, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "Active-HDL (Verilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "PrimeTime (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_timing_analysis
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_timing_analysis
set_global_assignment -name VERILOG_FILE testlist.v
set_location_assignment PIN_8 -to list[1]
set_location_assignment PIN_9 -to list[2]
set_location_assignment PIN_10 -to list[3]
set_location_assignment PIN_12 -to list[4]
set_location_assignment PIN_13 -to list[5]
set_location_assignment PIN_17 -to list[6]
set_location_assignment PIN_18 -to list[7]
set_location_assignment PIN_19 -to list[8]
set_location_assignment PIN_20 -to result[1]
set_location_assignment PIN_21 -to result[2]
set_location_assignment PIN_22 -to result[3]
set_location_assignment PIN_23 -to result[4]
set_location_assignment PIN_26 -to result[5]
set_location_assignment PIN_27 -to result[6]
set_location_assignment PIN_28 -to result[7]
set_location_assignment PIN_29 -to result[8]
set_global_assignment -name VECTOR_WAVEFORM_FILE testlist.vwf